* [PATCH 0/3] target/i386/hvf: Style cleanup
@ 2023-10-20 11:11 Philippe Mathieu-Daudé
2023-10-20 11:11 ` [PATCH 1/3] target/i386/hvf: Use CPUState typedef Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 11:11 UTC (permalink / raw)
To: qemu-devel
Cc: Cameron Esfahani, Zhao Liu, Roman Bolshakov,
Philippe Mathieu-Daudé
Keep HVF style closer to rest of target/i386/.
No functional changes.
Philippe Mathieu-Daudé (3):
target/i386/hvf: Use CPUState typedef
target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs'
target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu'
target/i386/hvf/x86_emu.c | 106 +++++++++++++++++++-------------------
1 file changed, 53 insertions(+), 53 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] target/i386/hvf: Use CPUState typedef
2023-10-20 11:11 [PATCH 0/3] target/i386/hvf: Style cleanup Philippe Mathieu-Daudé
@ 2023-10-20 11:11 ` Philippe Mathieu-Daudé
2023-10-20 15:11 ` Zhao Liu
2023-10-20 11:11 ` [PATCH 2/3] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs' Philippe Mathieu-Daudé
2023-10-20 11:11 ` [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Philippe Mathieu-Daudé
2 siblings, 1 reply; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 11:11 UTC (permalink / raw)
To: qemu-devel
Cc: Cameron Esfahani, Zhao Liu, Roman Bolshakov,
Philippe Mathieu-Daudé
Follow C style guidelines and use CPUState forward
declaration from "qemu/typedefs.h".
No functional changes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/hvf/x86_emu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index b1f8a685d1..cd7ef30126 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -45,7 +45,7 @@
#include "vmcs.h"
#include "vmx.h"
-void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
+void hvf_handle_io(CPUState *cpu, uint16_t port, void *data,
int direction, int size, uint32_t count);
#define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
@@ -1417,7 +1417,7 @@ static void init_cmd_handler()
}
}
-void load_regs(struct CPUState *cpu)
+void load_regs(CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
@@ -1440,7 +1440,7 @@ void load_regs(struct CPUState *cpu)
env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
}
-void store_regs(struct CPUState *cpu)
+void store_regs(CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
--
2.41.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs'
2023-10-20 11:11 [PATCH 0/3] target/i386/hvf: Style cleanup Philippe Mathieu-Daudé
2023-10-20 11:11 ` [PATCH 1/3] target/i386/hvf: Use CPUState typedef Philippe Mathieu-Daudé
@ 2023-10-20 11:11 ` Philippe Mathieu-Daudé
2023-10-20 15:14 ` Zhao Liu
2023-10-20 11:11 ` [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Philippe Mathieu-Daudé
2 siblings, 1 reply; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 11:11 UTC (permalink / raw)
To: qemu-devel
Cc: Cameron Esfahani, Zhao Liu, Roman Bolshakov,
Philippe Mathieu-Daudé
Follow the naming used by other files in target/i386/.
No functional changes.
Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/hvf/x86_emu.c | 92 +++++++++++++++++++--------------------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index cd7ef30126..5b82e84778 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -45,7 +45,7 @@
#include "vmcs.h"
#include "vmx.h"
-void hvf_handle_io(CPUState *cpu, uint16_t port, void *data,
+void hvf_handle_io(CPUState *cs, uint16_t port, void *data,
int direction, int size, uint32_t count);
#define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
@@ -666,13 +666,13 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
void simulate_rdmsr(CPUX86State *env)
{
X86CPU *x86_cpu = env_archcpu(env);
- CPUState *cpu = env_cpu(env);
+ CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
switch (msr) {
case MSR_IA32_TSC:
- val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET);
+ val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break;
case MSR_IA32_APICBASE:
val = cpu_get_apic_base(x86_cpu->apic_state);
@@ -681,16 +681,16 @@ void simulate_rdmsr(CPUX86State *env)
val = x86_cpu->ucode_rev;
break;
case MSR_EFER:
- val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER);
+ val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
break;
case MSR_FSBASE:
- val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE);
+ val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE);
break;
case MSR_GSBASE:
- val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE);
+ val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE);
break;
case MSR_KERNELGSBASE:
- val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE);
+ val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE);
break;
case MSR_STAR:
abort();
@@ -745,8 +745,8 @@ void simulate_rdmsr(CPUX86State *env)
val = env->mtrr_deftype;
break;
case MSR_CORE_THREAD_COUNT:
- val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */
- val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */
+ val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
+ val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
break;
default:
/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
@@ -767,7 +767,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
void simulate_wrmsr(CPUX86State *env)
{
X86CPU *x86_cpu = env_archcpu(env);
- CPUState *cpu = env_cpu(env);
+ CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@@ -778,13 +778,13 @@ void simulate_wrmsr(CPUX86State *env)
cpu_set_apic_base(x86_cpu->apic_state, data);
break;
case MSR_FSBASE:
- wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data);
+ wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
break;
case MSR_GSBASE:
- wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data);
+ wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data);
break;
case MSR_KERNELGSBASE:
- wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data);
+ wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data);
break;
case MSR_STAR:
abort();
@@ -796,10 +796,10 @@ void simulate_wrmsr(CPUX86State *env)
abort();
break;
case MSR_EFER:
- /*printf("new efer %llx\n", EFER(cpu));*/
- wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data);
+ /*printf("new efer %llx\n", EFER(cs));*/
+ wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data);
if (data & MSR_EFER_NXE) {
- hv_vcpu_invalidate_tlb(cpu->accel->fd);
+ hv_vcpu_invalidate_tlb(cs->accel->fd);
}
break;
case MSR_MTRRphysBase(0):
@@ -848,9 +848,9 @@ void simulate_wrmsr(CPUX86State *env)
/* Related to support known hypervisor interface */
/* if (g_hypervisor_iface)
- g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
+ g_hypervisor_iface->wrmsr_handler(cs, msr, data);
- printf("write msr %llx\n", RCX(cpu));*/
+ printf("write msr %llx\n", RCX(cs));*/
}
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
@@ -1417,56 +1417,56 @@ static void init_cmd_handler()
}
}
-void load_regs(CPUState *cpu)
+void load_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
+ X86CPU *x86_cpu = X86_CPU(cs);
CPUX86State *env = &x86_cpu->env;
int i = 0;
- RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX);
- RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX);
- RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX);
- RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX);
- RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI);
- RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI);
- RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP);
- RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP);
+ RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
+ RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
+ RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
+ RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
+ RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
+ RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
+ RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
+ RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
for (i = 8; i < 16; i++) {
- RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i);
+ RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
}
- env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS);
+ env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
rflags_to_lflags(env);
- env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
+ env->eip = rreg(cs->accel->fd, HV_X86_RIP);
}
-void store_regs(CPUState *cpu)
+void store_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
+ X86CPU *x86_cpu = X86_CPU(cs);
CPUX86State *env = &x86_cpu->env;
int i = 0;
- wreg(cpu->accel->fd, HV_X86_RAX, RAX(env));
- wreg(cpu->accel->fd, HV_X86_RBX, RBX(env));
- wreg(cpu->accel->fd, HV_X86_RCX, RCX(env));
- wreg(cpu->accel->fd, HV_X86_RDX, RDX(env));
- wreg(cpu->accel->fd, HV_X86_RSI, RSI(env));
- wreg(cpu->accel->fd, HV_X86_RDI, RDI(env));
- wreg(cpu->accel->fd, HV_X86_RBP, RBP(env));
- wreg(cpu->accel->fd, HV_X86_RSP, RSP(env));
+ wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
+ wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
+ wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
+ wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
+ wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
+ wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
+ wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
+ wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
for (i = 8; i < 16; i++) {
- wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i));
+ wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
}
lflags_to_rflags(env);
- wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags);
- macvm_set_rip(cpu, env->eip);
+ wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
+ macvm_set_rip(cs, env->eip);
}
bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
{
- /*if (hvf_vcpu_id(cpu))
- printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip,
+ /*if (hvf_vcpu_id(cs))
+ printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cs), env->eip,
decode_cmd_to_string(ins->cmd));*/
if (!_cmd_handler[ins->cmd].handler) {
--
2.41.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu'
2023-10-20 11:11 [PATCH 0/3] target/i386/hvf: Style cleanup Philippe Mathieu-Daudé
2023-10-20 11:11 ` [PATCH 1/3] target/i386/hvf: Use CPUState typedef Philippe Mathieu-Daudé
2023-10-20 11:11 ` [PATCH 2/3] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs' Philippe Mathieu-Daudé
@ 2023-10-20 11:11 ` Philippe Mathieu-Daudé
2023-10-20 15:15 ` Zhao Liu
2 siblings, 1 reply; 7+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 11:11 UTC (permalink / raw)
To: qemu-devel
Cc: Cameron Esfahani, Zhao Liu, Roman Bolshakov,
Philippe Mathieu-Daudé
Follow the naming used by other files in target/i386/.
No functional changes.
Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/hvf/x86_emu.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index 5b82e84778..3a3f0a50d0 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
void simulate_rdmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = env_archcpu(env);
+ X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
@@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env)
val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break;
case MSR_IA32_APICBASE:
- val = cpu_get_apic_base(x86_cpu->apic_state);
+ val = cpu_get_apic_base(cpu->apic_state);
break;
case MSR_IA32_UCODE_REV:
- val = x86_cpu->ucode_rev;
+ val = cpu->ucode_rev;
break;
case MSR_EFER:
val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
@@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
void simulate_wrmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = env_archcpu(env);
+ X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env)
case MSR_IA32_TSC:
break;
case MSR_IA32_APICBASE:
- cpu_set_apic_base(x86_cpu->apic_state, data);
+ cpu_set_apic_base(cpu->apic_state, data);
break;
case MSR_FSBASE:
wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
@@ -1419,8 +1419,8 @@ static void init_cmd_handler()
void load_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cs);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int i = 0;
RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
@@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs)
void store_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cs);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int i = 0;
wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
--
2.41.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] target/i386/hvf: Use CPUState typedef
2023-10-20 11:11 ` [PATCH 1/3] target/i386/hvf: Use CPUState typedef Philippe Mathieu-Daudé
@ 2023-10-20 15:11 ` Zhao Liu
0 siblings, 0 replies; 7+ messages in thread
From: Zhao Liu @ 2023-10-20 15:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, Cameron Esfahani, Roman Bolshakov
On Fri, Oct 20, 2023 at 01:11:34PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 20 Oct 2023 13:11:34 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH 1/3] target/i386/hvf: Use CPUState typedef
> X-Mailer: git-send-email 2.41.0
>
> Follow C style guidelines and use CPUState forward
> declaration from "qemu/typedefs.h".
>
> No functional changes.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/i386/hvf/x86_emu.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
>
> diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
> index b1f8a685d1..cd7ef30126 100644
> --- a/target/i386/hvf/x86_emu.c
> +++ b/target/i386/hvf/x86_emu.c
> @@ -45,7 +45,7 @@
> #include "vmcs.h"
> #include "vmx.h"
>
> -void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
> +void hvf_handle_io(CPUState *cpu, uint16_t port, void *data,
> int direction, int size, uint32_t count);
>
> #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
> @@ -1417,7 +1417,7 @@ static void init_cmd_handler()
> }
> }
>
> -void load_regs(struct CPUState *cpu)
> +void load_regs(CPUState *cpu)
> {
> X86CPU *x86_cpu = X86_CPU(cpu);
> CPUX86State *env = &x86_cpu->env;
> @@ -1440,7 +1440,7 @@ void load_regs(struct CPUState *cpu)
> env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
> }
>
> -void store_regs(struct CPUState *cpu)
> +void store_regs(CPUState *cpu)
> {
> X86CPU *x86_cpu = X86_CPU(cpu);
> CPUX86State *env = &x86_cpu->env;
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs'
2023-10-20 11:11 ` [PATCH 2/3] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs' Philippe Mathieu-Daudé
@ 2023-10-20 15:14 ` Zhao Liu
0 siblings, 0 replies; 7+ messages in thread
From: Zhao Liu @ 2023-10-20 15:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, Cameron Esfahani, Roman Bolshakov
On Fri, Oct 20, 2023 at 01:11:35PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 20 Oct 2023 13:11:35 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH 2/3] target/i386/hvf: Rename 'CPUState *cpu' variable as
> 'cs'
> X-Mailer: git-send-email 2.41.0
>
> Follow the naming used by other files in target/i386/.
>
> No functional changes.
>
> Suggested-by: Zhao Liu <zhao1.liu@intel.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/i386/hvf/x86_emu.c | 92 +++++++++++++++++++--------------------
> 1 file changed, 46 insertions(+), 46 deletions(-)
Thanks!
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
>
> diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
> index cd7ef30126..5b82e84778 100644
> --- a/target/i386/hvf/x86_emu.c
> +++ b/target/i386/hvf/x86_emu.c
> @@ -45,7 +45,7 @@
> #include "vmcs.h"
> #include "vmx.h"
>
> -void hvf_handle_io(CPUState *cpu, uint16_t port, void *data,
> +void hvf_handle_io(CPUState *cs, uint16_t port, void *data,
> int direction, int size, uint32_t count);
>
> #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
> @@ -666,13 +666,13 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
> void simulate_rdmsr(CPUX86State *env)
> {
> X86CPU *x86_cpu = env_archcpu(env);
> - CPUState *cpu = env_cpu(env);
> + CPUState *cs = env_cpu(env);
> uint32_t msr = ECX(env);
> uint64_t val = 0;
>
> switch (msr) {
> case MSR_IA32_TSC:
> - val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET);
> + val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
> break;
> case MSR_IA32_APICBASE:
> val = cpu_get_apic_base(x86_cpu->apic_state);
> @@ -681,16 +681,16 @@ void simulate_rdmsr(CPUX86State *env)
> val = x86_cpu->ucode_rev;
> break;
> case MSR_EFER:
> - val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER);
> + val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
> break;
> case MSR_FSBASE:
> - val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE);
> + val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE);
> break;
> case MSR_GSBASE:
> - val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE);
> + val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE);
> break;
> case MSR_KERNELGSBASE:
> - val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE);
> + val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE);
> break;
> case MSR_STAR:
> abort();
> @@ -745,8 +745,8 @@ void simulate_rdmsr(CPUX86State *env)
> val = env->mtrr_deftype;
> break;
> case MSR_CORE_THREAD_COUNT:
> - val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */
> - val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */
> + val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
> + val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
> break;
> default:
> /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
> @@ -767,7 +767,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
> void simulate_wrmsr(CPUX86State *env)
> {
> X86CPU *x86_cpu = env_archcpu(env);
> - CPUState *cpu = env_cpu(env);
> + CPUState *cs = env_cpu(env);
> uint32_t msr = ECX(env);
> uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
>
> @@ -778,13 +778,13 @@ void simulate_wrmsr(CPUX86State *env)
> cpu_set_apic_base(x86_cpu->apic_state, data);
> break;
> case MSR_FSBASE:
> - wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data);
> + wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
> break;
> case MSR_GSBASE:
> - wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data);
> + wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data);
> break;
> case MSR_KERNELGSBASE:
> - wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data);
> + wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data);
> break;
> case MSR_STAR:
> abort();
> @@ -796,10 +796,10 @@ void simulate_wrmsr(CPUX86State *env)
> abort();
> break;
> case MSR_EFER:
> - /*printf("new efer %llx\n", EFER(cpu));*/
> - wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data);
> + /*printf("new efer %llx\n", EFER(cs));*/
> + wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data);
> if (data & MSR_EFER_NXE) {
> - hv_vcpu_invalidate_tlb(cpu->accel->fd);
> + hv_vcpu_invalidate_tlb(cs->accel->fd);
> }
> break;
> case MSR_MTRRphysBase(0):
> @@ -848,9 +848,9 @@ void simulate_wrmsr(CPUX86State *env)
>
> /* Related to support known hypervisor interface */
> /* if (g_hypervisor_iface)
> - g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
> + g_hypervisor_iface->wrmsr_handler(cs, msr, data);
>
> - printf("write msr %llx\n", RCX(cpu));*/
> + printf("write msr %llx\n", RCX(cs));*/
> }
>
> static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
> @@ -1417,56 +1417,56 @@ static void init_cmd_handler()
> }
> }
>
> -void load_regs(CPUState *cpu)
> +void load_regs(CPUState *cs)
> {
> - X86CPU *x86_cpu = X86_CPU(cpu);
> + X86CPU *x86_cpu = X86_CPU(cs);
> CPUX86State *env = &x86_cpu->env;
>
> int i = 0;
> - RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX);
> - RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX);
> - RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX);
> - RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX);
> - RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI);
> - RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI);
> - RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP);
> - RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP);
> + RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
> + RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
> + RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
> + RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
> + RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
> + RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
> + RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
> + RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
> for (i = 8; i < 16; i++) {
> - RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i);
> + RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
> }
>
> - env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS);
> + env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
> rflags_to_lflags(env);
> - env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
> + env->eip = rreg(cs->accel->fd, HV_X86_RIP);
> }
>
> -void store_regs(CPUState *cpu)
> +void store_regs(CPUState *cs)
> {
> - X86CPU *x86_cpu = X86_CPU(cpu);
> + X86CPU *x86_cpu = X86_CPU(cs);
> CPUX86State *env = &x86_cpu->env;
>
> int i = 0;
> - wreg(cpu->accel->fd, HV_X86_RAX, RAX(env));
> - wreg(cpu->accel->fd, HV_X86_RBX, RBX(env));
> - wreg(cpu->accel->fd, HV_X86_RCX, RCX(env));
> - wreg(cpu->accel->fd, HV_X86_RDX, RDX(env));
> - wreg(cpu->accel->fd, HV_X86_RSI, RSI(env));
> - wreg(cpu->accel->fd, HV_X86_RDI, RDI(env));
> - wreg(cpu->accel->fd, HV_X86_RBP, RBP(env));
> - wreg(cpu->accel->fd, HV_X86_RSP, RSP(env));
> + wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
> + wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
> + wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
> + wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
> + wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
> + wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
> + wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
> + wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
> for (i = 8; i < 16; i++) {
> - wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i));
> + wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
> }
>
> lflags_to_rflags(env);
> - wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags);
> - macvm_set_rip(cpu, env->eip);
> + wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
> + macvm_set_rip(cs, env->eip);
> }
>
> bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
> {
> - /*if (hvf_vcpu_id(cpu))
> - printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip,
> + /*if (hvf_vcpu_id(cs))
> + printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cs), env->eip,
> decode_cmd_to_string(ins->cmd));*/
>
> if (!_cmd_handler[ins->cmd].handler) {
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu'
2023-10-20 11:11 ` [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Philippe Mathieu-Daudé
@ 2023-10-20 15:15 ` Zhao Liu
0 siblings, 0 replies; 7+ messages in thread
From: Zhao Liu @ 2023-10-20 15:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, Cameron Esfahani, Roman Bolshakov
On Fri, Oct 20, 2023 at 01:11:36PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 20 Oct 2023 13:11:36 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as
> 'cpu'
> X-Mailer: git-send-email 2.41.0
>
> Follow the naming used by other files in target/i386/.
>
> No functional changes.
>
> Suggested-by: Zhao Liu <zhao1.liu@intel.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/i386/hvf/x86_emu.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
Thanks!
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
>
> diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
> index 5b82e84778..3a3f0a50d0 100644
> --- a/target/i386/hvf/x86_emu.c
> +++ b/target/i386/hvf/x86_emu.c
> @@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
>
> void simulate_rdmsr(CPUX86State *env)
> {
> - X86CPU *x86_cpu = env_archcpu(env);
> + X86CPU *cpu = env_archcpu(env);
> CPUState *cs = env_cpu(env);
> uint32_t msr = ECX(env);
> uint64_t val = 0;
> @@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env)
> val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
> break;
> case MSR_IA32_APICBASE:
> - val = cpu_get_apic_base(x86_cpu->apic_state);
> + val = cpu_get_apic_base(cpu->apic_state);
> break;
> case MSR_IA32_UCODE_REV:
> - val = x86_cpu->ucode_rev;
> + val = cpu->ucode_rev;
> break;
> case MSR_EFER:
> val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
> @@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
>
> void simulate_wrmsr(CPUX86State *env)
> {
> - X86CPU *x86_cpu = env_archcpu(env);
> + X86CPU *cpu = env_archcpu(env);
> CPUState *cs = env_cpu(env);
> uint32_t msr = ECX(env);
> uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
> @@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env)
> case MSR_IA32_TSC:
> break;
> case MSR_IA32_APICBASE:
> - cpu_set_apic_base(x86_cpu->apic_state, data);
> + cpu_set_apic_base(cpu->apic_state, data);
> break;
> case MSR_FSBASE:
> wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
> @@ -1419,8 +1419,8 @@ static void init_cmd_handler()
>
> void load_regs(CPUState *cs)
> {
> - X86CPU *x86_cpu = X86_CPU(cs);
> - CPUX86State *env = &x86_cpu->env;
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
>
> int i = 0;
> RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
> @@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs)
>
> void store_regs(CPUState *cs)
> {
> - X86CPU *x86_cpu = X86_CPU(cs);
> - CPUX86State *env = &x86_cpu->env;
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
>
> int i = 0;
> wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-10-20 15:04 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-20 11:11 [PATCH 0/3] target/i386/hvf: Style cleanup Philippe Mathieu-Daudé
2023-10-20 11:11 ` [PATCH 1/3] target/i386/hvf: Use CPUState typedef Philippe Mathieu-Daudé
2023-10-20 15:11 ` Zhao Liu
2023-10-20 11:11 ` [PATCH 2/3] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs' Philippe Mathieu-Daudé
2023-10-20 15:14 ` Zhao Liu
2023-10-20 11:11 ` [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Philippe Mathieu-Daudé
2023-10-20 15:15 ` Zhao Liu
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