From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A43DC25B48 for ; Thu, 26 Oct 2023 06:49:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvuAa-00049e-MD; Thu, 26 Oct 2023 02:48:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvuAY-00049C-FG for qemu-devel@nongnu.org; Thu, 26 Oct 2023 02:48:38 -0400 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvuAV-0000G4-A9 for qemu-devel@nongnu.org; Thu, 26 Oct 2023 02:48:38 -0400 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39Q6mM6A016730; Thu, 26 Oct 2023 14:48:22 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from ethan84-VirtualBox (10.0.12.51) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 26 Oct 2023 14:48:20 +0800 Date: Thu, 26 Oct 2023 14:48:14 +0800 To: Peter Xu CC: , Paolo Bonzini , "David Hildenbrand" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented Message-ID: References: <20231025051430.493079-1-ethan84@andestech.com> <20231025051430.493079-3-ethan84@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.1.4 (2021-12-11) X-Originating-IP: [10.0.12.51] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39Q6mM6A016730 Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Oct 25, 2023 at 11:14:42AM -0400, Peter Xu wrote: > On Wed, Oct 25, 2023 at 01:14:26PM +0800, Ethan Chen wrote: > > Signed-off-by: Ethan Chen > > --- > > system/physmem.c | 9 +++++++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/system/physmem.c b/system/physmem.c > > index fc2b0fee01..53b6ab735c 100644 > > --- a/system/physmem.c > > +++ b/system/physmem.c > > @@ -432,8 +432,13 @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm > > iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); > > } > > > > - iotlb = imrc->translate(iommu_mr, addr, is_write ? > > - IOMMU_WO : IOMMU_RO, iommu_idx); > > + if (imrc->translate_size) { > > + iotlb = imrc->translate_size(iommu_mr, addr, *plen_out, is_write ? > > + IOMMU_WO : IOMMU_RO, iommu_idx); > > + } else { > > + iotlb = imrc->translate(iommu_mr, addr, is_write ? > > + IOMMU_WO : IOMMU_RO, iommu_idx); > > + } > > Currently the translation size is encoded in iotlb.addr_mask. Can riscv do > the same? Riscv do the same, so translation size may be reduced by iotlb.addr_mask. > > For example, lookup addr in match_entry_md() ranges, report size back into > iotlb.addr_mask, rather than enforcing *plen_out range always resides in > one translation only. > > IMHO it's actually legal if *plen_out covers more than one IOMMU > translations. QEMU memory core should have taken care of that by > separately translate the ranges and apply RW on top. With current proposal > of translate_size() I think it'll fail instead, which is not wanted. > My target is to support IOPMP partially hit error. IOPMP checks whole memory access region is in the same entry. If not, reject the access instead of modify the access size. Because most of IOPMP permisson checking features can be implemented by current IOMMU class, so I add this function in IOMMU class. There may be other more suitable ways to support partially hit error. > Thanks, > > -- > Peter Xu > Thanks, Ethan Chen From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qvuAZ-00049L-NC for mharc-qemu-devel@gnu.org; Thu, 26 Oct 2023 02:48:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvuAY-00049C-FG for qemu-devel@nongnu.org; Thu, 26 Oct 2023 02:48:38 -0400 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvuAV-0000G4-A9 for qemu-devel@nongnu.org; Thu, 26 Oct 2023 02:48:38 -0400 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39Q6mM6A016730; Thu, 26 Oct 2023 14:48:22 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from ethan84-VirtualBox (10.0.12.51) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 26 Oct 2023 14:48:20 +0800 Date: Thu, 26 Oct 2023 14:48:14 +0800 From: Ethan Chen To: Peter Xu CC: , Paolo Bonzini , "David Hildenbrand" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented Message-ID: References: <20231025051430.493079-1-ethan84@andestech.com> <20231025051430.493079-3-ethan84@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.1.4 (2021-12-11) X-Originating-IP: [10.0.12.51] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 39Q6mM6A016730 Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2023 06:48:38 -0000 Message-ID: <20231026064814.pVdf3BuPfzWh2oUsLQliqdJXLcWk9nqkDgkKhQYsRHg@z> On Wed, Oct 25, 2023 at 11:14:42AM -0400, Peter Xu wrote: > On Wed, Oct 25, 2023 at 01:14:26PM +0800, Ethan Chen wrote: > > Signed-off-by: Ethan Chen > > --- > > system/physmem.c | 9 +++++++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/system/physmem.c b/system/physmem.c > > index fc2b0fee01..53b6ab735c 100644 > > --- a/system/physmem.c > > +++ b/system/physmem.c > > @@ -432,8 +432,13 @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm > > iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); > > } > > > > - iotlb = imrc->translate(iommu_mr, addr, is_write ? > > - IOMMU_WO : IOMMU_RO, iommu_idx); > > + if (imrc->translate_size) { > > + iotlb = imrc->translate_size(iommu_mr, addr, *plen_out, is_write ? > > + IOMMU_WO : IOMMU_RO, iommu_idx); > > + } else { > > + iotlb = imrc->translate(iommu_mr, addr, is_write ? > > + IOMMU_WO : IOMMU_RO, iommu_idx); > > + } > > Currently the translation size is encoded in iotlb.addr_mask. Can riscv do > the same? Riscv do the same, so translation size may be reduced by iotlb.addr_mask. > > For example, lookup addr in match_entry_md() ranges, report size back into > iotlb.addr_mask, rather than enforcing *plen_out range always resides in > one translation only. > > IMHO it's actually legal if *plen_out covers more than one IOMMU > translations. QEMU memory core should have taken care of that by > separately translate the ranges and apply RW on top. With current proposal > of translate_size() I think it'll fail instead, which is not wanted. > My target is to support IOPMP partially hit error. IOPMP checks whole memory access region is in the same entry. If not, reject the access instead of modify the access size. Because most of IOPMP permisson checking features can be implemented by current IOMMU class, so I add this function in IOMMU class. There may be other more suitable ways to support partially hit error. > Thanks, > > -- > Peter Xu > Thanks, Ethan Chen