qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Sunil V L <sunilvl@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
	"Shannon Zhao" <shannon.zhaosl@gmail.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Ani Sinha" <anisinha@redhat.com>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Gerd Hoffmann" <kraxel@redhat.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Weiwei Li" <liweiwei@iscas.ac.cn>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Haibo Xu" <haibo1.xu@intel.com>
Subject: Re: [PATCH v4 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
Date: Thu, 26 Oct 2023 18:03:02 +0530	[thread overview]
Message-ID: <ZTpcfq+96YVE5WCl@sunil-laptop> (raw)
In-Reply-To: <20231026-5530c164173cd1859e9df666@orel>

On Thu, Oct 26, 2023 at 10:31:51AM +0200, Andrew Jones wrote:
> On Thu, Oct 26, 2023 at 01:37:09AM +0530, Sunil V L wrote:
> > MMU type information is available via MMU node in RHCT. Add this node in
> > RHCT.
> > 
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> > ---
> >  hw/riscv/virt-acpi-build.c | 37 ++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 36 insertions(+), 1 deletion(-)
> > 
> > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> > index ebe7062b9b..dc7c0213f5 100644
> > --- a/hw/riscv/virt-acpi-build.c
> > +++ b/hw/riscv/virt-acpi-build.c
> > @@ -159,6 +159,8 @@ static void build_rhct(GArray *table_data,
> >      size_t len, aligned_len;
> >      uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
> >      RISCVCPU *cpu = &s->soc[0].harts[0];
> > +    uint32_t mmu_offset = 0;
> > +    uint8_t satp_mode_max;
> >      char *isa;
> >  
> >      AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> > @@ -178,6 +180,10 @@ static void build_rhct(GArray *table_data,
> >          num_rhct_nodes++;
> >      }
> >  
> > +    if (cpu->cfg.satp_mode.supported != 0) {
> > +        num_rhct_nodes++;
> > +    }
> > +
> >      /* Number of RHCT nodes*/
> >      build_append_int_noprefix(table_data, num_rhct_nodes, 4);
> >  
> > @@ -233,6 +239,26 @@ static void build_rhct(GArray *table_data,
> >          }
> >      }
> >  
> > +    /* MMU node structure */
> > +    if (cpu->cfg.satp_mode.supported != 0) {
> > +        satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> > +        mmu_offset = table_data->len - table.table_offset;
> > +        build_append_int_noprefix(table_data, 2, 2);    /* Type */
> > +        build_append_int_noprefix(table_data, 8, 2);    /* Length */
> > +        build_append_int_noprefix(table_data, 0x1, 2);  /* Revision */
> > +        build_append_int_noprefix(table_data, 0, 1);    /* Reserved */
> > +        /* MMU Type */
> > +        if (satp_mode_max == VM_1_10_SV57) {
> > +            build_append_int_noprefix(table_data, 2, 1);    /* Sv57 */
> > +        } else if (satp_mode_max == VM_1_10_SV48) {
> > +            build_append_int_noprefix(table_data, 1, 1);    /* Sv48 */
> > +        } else if (satp_mode_max == VM_1_10_SV39) {
> > +            build_append_int_noprefix(table_data, 0, 1);    /* Sv39 */
> > +        } else {
> > +            assert(1);
> > +        }
> > +    }
> > +
> >      /* Hart Info Node */
> >      for (int i = 0; i < arch_ids->len; i++) {
> >          len = 16;
> > @@ -245,17 +271,26 @@ static void build_rhct(GArray *table_data,
> >              num_offsets++;
> >          }
> >  
> > +        if (mmu_offset) {
> > +            len += 4;
> > +            num_offsets++;
> > +        }
> > +
> >          build_append_int_noprefix(table_data, len, 2);
> >          build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> >          /* Number of offsets */
> >          build_append_int_noprefix(table_data, num_offsets, 2);
> >          build_append_int_noprefix(table_data, i, 4);   /* ACPI Processor UID */
> > -
> >          /* Offsets */
> >          build_append_int_noprefix(table_data, isa_offset, 4);
> > +        if (mmu_offset) {
> > +            build_append_int_noprefix(table_data, mmu_offset, 4);
> > +        }
> > +
> 
> In the previous version of this patch the MMU node was getting generated
> above the CMO node, so its offset was less than those of the CMO node,
> and why I recommended moving it up here. But, in this version, the MMU
> node is now getting generated after the CMO node, so moving this up
> means the offsets are still not in ascending order.
> 
Yeah, after changing here I realized MMU node type is logically better
to be created after cmo. So, I changed the creation order but forgot
reorder here. Will update in the next revision.

Thanks,
Sunil


  reply	other threads:[~2023-10-26 12:34 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-25 20:07 [PATCH v4 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
2023-10-25 20:07 ` [PATCH v4 01/13] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
2023-10-26  8:15   ` Andrew Jones
2023-10-26 12:30     ` Sunil V L
2023-10-25 20:07 ` [PATCH v4 02/13] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
2023-10-25 20:07 ` [PATCH v4 03/13] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT Sunil V L
2023-10-30  2:21   ` Alistair Francis
2023-10-25 20:07 ` [PATCH v4 04/13] hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L
2023-10-25 20:07 ` [PATCH v4 05/13] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L
2023-10-26  8:46   ` Andrew Jones
2023-10-26 12:38     ` Sunil V L
2023-10-25 20:07 ` [PATCH v4 06/13] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
2023-10-25 20:07 ` [PATCH v4 07/13] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
2023-10-25 20:07 ` [PATCH v4 08/13] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
2023-10-25 20:07 ` [PATCH v4 09/13] hw/riscv/virt-acpi-build.c: Add MMU node " Sunil V L
2023-10-26  8:31   ` Andrew Jones
2023-10-26 12:33     ` Sunil V L [this message]
2023-10-25 20:07 ` [PATCH v4 10/13] hw/pci-host/gpex: Define properties for MMIO ranges Sunil V L
2023-10-30  2:25   ` Alistair Francis
2023-10-25 20:07 ` [PATCH v4 11/13] hw/riscv/virt: Update GPEX MMIO related properties Sunil V L
2023-10-30  2:50   ` Alistair Francis
2023-10-25 20:07 ` [PATCH v4 12/13] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Sunil V L
2023-10-30  3:06   ` Alistair Francis
2023-10-25 20:07 ` [PATCH v4 13/13] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
2023-10-30  3:07   ` Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZTpcfq+96YVE5WCl@sunil-laptop \
    --to=sunilvl@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=alistair.francis@wdc.com \
    --cc=anisinha@redhat.com \
    --cc=apatel@ventanamicro.com \
    --cc=atishp@rivosinc.com \
    --cc=bin.meng@windriver.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=eduardo@habkost.net \
    --cc=haibo1.xu@intel.com \
    --cc=imammedo@redhat.com \
    --cc=kraxel@redhat.com \
    --cc=liweiwei@iscas.ac.cn \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=mst@redhat.com \
    --cc=palmer@dabbelt.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=philmd@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=shannon.zhaosl@gmail.com \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).