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From: Ethan Chen via <qemu-devel@nongnu.org>
To: Peter Xu <peterx@redhat.com>
Cc: qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented
Date: Fri, 27 Oct 2023 11:28:36 +0800	[thread overview]
Message-ID: <ZTsuZLMOLsehgzoc@ethan84-VirtualBox> (raw)
In-Reply-To: <ZTkw4itrYANXm4qR@x1n>

On Thu, Oct 26, 2023 at 10:20:41AM -0400, Peter Xu wrote:
> Could you elaborate why is that important?  In what use case?
I was not involved in the formulation of the IOPMP specification, but I'll try
to explain my perspective. IOPMP use the same the idea as PMP. "The matching 
PMP entry must match all bytes of an access, or the access fails."

> 
> Consider IOVA mapped for address range iova=[0, 4K] only, here we have a
> DMA request with range=[0, 8K].  Now my understanding is what you want to
> achieve is don't trigger the DMA to [0, 4K] and fail the whole [0, 8K]
> request.
> 
> Can we just fail at the latter DMA [4K, 8K] when it happens?  After all,
> IIUC a device can split the 0-8K DMA into two smaller DMAs, then the 1st
> chunk can succeed then if it falls in 0-4K.  Some further explanation of
> the failure use case could be helpful.

IOPMP can only detect partially hit in an access. DMA device will split a 
large DMA transfer to small DMA transfers base on target and DMA transfer 
width, so partially hit error only happens when an access cross the boundary.
But to ensure that an access is only within one entry is still important. 
For example, an entry may mean permission of a device memory region. We do 
not want to see one DMA transfer can access mutilple devices, although DMA 
have permissions from multiple entries.

Thanks,
Ethan Chen


WARNING: multiple messages have this Message-ID (diff)
From: Ethan Chen <ethan84@andestech.com>
To: Peter Xu <peterx@redhat.com>
Cc: qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented
Date: Fri, 27 Oct 2023 11:28:36 +0800	[thread overview]
Message-ID: <ZTsuZLMOLsehgzoc@ethan84-VirtualBox> (raw)
Message-ID: <20231027032836.vGyULlHnDS3oEN_Bj_6fW3beHODYka6hlhHiUPwlFmo@z> (raw)
In-Reply-To: <ZTkw4itrYANXm4qR@x1n>

On Thu, Oct 26, 2023 at 10:20:41AM -0400, Peter Xu wrote:
> Could you elaborate why is that important?  In what use case?
I was not involved in the formulation of the IOPMP specification, but I'll try
to explain my perspective. IOPMP use the same the idea as PMP. "The matching 
PMP entry must match all bytes of an access, or the access fails."

> 
> Consider IOVA mapped for address range iova=[0, 4K] only, here we have a
> DMA request with range=[0, 8K].  Now my understanding is what you want to
> achieve is don't trigger the DMA to [0, 4K] and fail the whole [0, 8K]
> request.
> 
> Can we just fail at the latter DMA [4K, 8K] when it happens?  After all,
> IIUC a device can split the 0-8K DMA into two smaller DMAs, then the 1st
> chunk can succeed then if it falls in 0-4K.  Some further explanation of
> the failure use case could be helpful.

IOPMP can only detect partially hit in an access. DMA device will split a 
large DMA transfer to small DMA transfers base on target and DMA transfer 
width, so partially hit error only happens when an access cross the boundary.
But to ensure that an access is only within one entry is still important. 
For example, an entry may mean permission of a device memory region. We do 
not want to see one DMA transfer can access mutilple devices, although DMA 
have permissions from multiple entries.

Thanks,
Ethan Chen


  parent reply	other threads:[~2023-10-27  3:29 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-25  5:14 [PATCH 0/6] Support RISC-V IOPMP Ethan Chen via
2023-10-25  5:14 ` Ethan Chen
2023-10-25  5:14 ` [PATCH 1/6] exec/memory: Introduce the translate_size function within the IOMMU class Ethan Chen via
2023-10-25  5:14   ` Ethan Chen
2023-10-25 14:56   ` David Hildenbrand
2023-10-26  7:14     ` Ethan Chen via
2023-10-26  7:14       ` Ethan Chen
2023-10-26  7:26       ` David Hildenbrand
2023-10-25  5:14 ` [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented Ethan Chen via
2023-10-25  5:14   ` Ethan Chen
2023-10-25 15:14   ` Peter Xu
2023-10-26  6:48     ` Ethan Chen via
2023-10-26  6:48       ` Ethan Chen
2023-10-26 14:20       ` Peter Xu
2023-10-27  3:28     ` Ethan Chen via [this message]
2023-10-27  3:28       ` Ethan Chen
2023-10-27 16:02       ` Peter Xu
2023-10-27 16:13         ` Peter Xu
2023-10-30  6:00         ` Ethan Chen via
2023-10-30  6:00           ` Ethan Chen
2023-10-30 15:02           ` Peter Xu
2023-10-31  8:52             ` Ethan Chen via
2023-10-31  8:52               ` Ethan Chen
2023-10-25  5:14 ` [PATCH 3/6] exec/memattrs: Add iopmp source id to MemTxAttrs Ethan Chen via
2023-10-25  5:14   ` Ethan Chen
2023-10-25  5:14 ` [PATCH 4/6] Add RISC-V IOPMP support Ethan Chen via
2023-10-25  5:14   ` Ethan Chen
2023-10-25  5:14 ` [PATCH 5/6] hw/dma: Add Andes ATCDMAC300 support Ethan Chen via
2023-10-25  5:14   ` Ethan Chen
2023-10-25  5:14 ` [PATCH 6/6] hw/riscv/virt: Add IOPMP support Ethan Chen via
2023-10-25  5:14   ` Ethan Chen
2023-10-26 12:02 ` [PATCH 0/6] Support RISC-V IOPMP Ethan Chen via
2023-10-26 12:02   ` Ethan Chen

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