From: Ethan Chen via <qemu-devel@nongnu.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Peter Xu <peterx@redhat.com>, <qemu-devel@nongnu.org>,
<richard.henderson@linaro.org>, <pbonzini@redhat.com>,
<palmer@dabbelt.com>, <alistair.francis@wdc.com>,
<in.meng@windriver.com>, <liweiwei@iscas.ac.cn>,
<dbarboza@ventanamicro.com>, <hiwei_liu@linux.alibaba.com>,
<qemu-riscv@nongnu.org>, <david@redhat.com>
Subject: Re: [PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs
Date: Mon, 6 Nov 2023 09:56:45 +0800 [thread overview]
Message-ID: <ZUhH3Rulnj64whB4@ethan84-VirtualBox> (raw)
In-Reply-To: <CAFEAcA-1dJnsDyZpf2Dy9XuAdp6CFWSFCzV7eceUJ6RyFLaVPA@mail.gmail.com>
On Fri, Nov 03, 2023 at 10:34:28AM +0000, Peter Maydell wrote:
> On Fri, 3 Nov 2023 at 03:29, Ethan Chen <ethan84@andestech.com> wrote:
> >
> > On Thu, Nov 02, 2023 at 01:53:05PM +0000, Peter Maydell wrote:
> > > On Thu, 2 Nov 2023 at 13:49, Peter Xu <peterx@redhat.com> wrote:
> > > >
> > > > On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan Chen wrote:
> > > > > Signed-off-by: Ethan Chen <ethan84@andestech.com>
> > > > > ---
> > > > > include/exec/memattrs.h | 6 ++++++
> > > > > 1 file changed, 6 insertions(+)
> > > > >
> > > > > diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
> > > > > index d04170aa27..fc15e5d7d3 100644
> > > > > --- a/include/exec/memattrs.h
> > > > > +++ b/include/exec/memattrs.h
> > > > > @@ -64,6 +64,12 @@ typedef struct MemTxAttrs {
> > > > > unsigned int target_tlb_bit0 : 1;
> > > > > unsigned int target_tlb_bit1 : 1;
> > > > > unsigned int target_tlb_bit2 : 1;
> > > > > +
> > > > > + /* IOPMP support up to 65535 sources */
> > > > > + unsigned int iopmp_sid:16;
> > > >
> > > > There's MemTxAttrs.requester_id, SID for pci, same length. Reuse it?
> > > >
> > > > > + /* Transaction infomation for IOPMP */
> > > > > + unsigned long long iopmp_start_addr;
> > > > > + unsigned long long iopmp_end_addr;
> > > >
> > > > PS: encoding addresses into memattrs is.. strange, but since I know nothing
> > > > about iopmp, I'll leave that for other reviewers.
> > > >
> > > > Currently MemTxAttrs are passed as a whole int on the stack, if it keeps
> > > > growing we may start to consider a pointer, but need to check the side
> > > > effects of unexpected fields modified within a call.
> > >
> > > Yeah, this struct is intended to model the various attributes that
> > > get passed around on the bus alongside data in real hardware.
> > > I'm pretty sure no real hardware is passing around start and
> > > end transaction addresses on its bus with every read and
> > > write, which suggests that we should be doing this some other
> > > way than adding these fields to the MemTxAttrs struct.
> >
> > For AXI bus ADDR, LEN, SIZE are signals in read/write address channel.
> > IOPMP will check that start address = ADDR,
> > and end address = ADDR + LEN * SIZE.
>
> Yes, but you don't pass the start and end address on the AXI
> bus, so they don't go in QEMU's MemTxAttrs either.
I will add those AXI bus signals to MemTxAttrs instead of using start and end
address in next revision.
Thanks,
Ethan Chen
next prev parent reply other threads:[~2023-11-06 1:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-02 9:40 [PATCH v2 0/4] Support RISC-V IOPMP Ethan Chen via
2023-11-02 9:40 ` [PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs Ethan Chen via
2023-11-02 13:49 ` Peter Xu
2023-11-02 13:53 ` Peter Maydell
2023-11-03 3:29 ` Ethan Chen via
2023-11-03 10:34 ` Peter Maydell
2023-11-06 1:56 ` Ethan Chen via [this message]
2023-11-06 10:34 ` Peter Maydell
2023-11-07 3:01 ` Ethan Chen via
2023-11-07 10:53 ` Peter Maydell
2023-11-08 7:33 ` Ethan Chen via
2023-11-03 3:27 ` Ethan Chen via
2023-11-02 9:40 ` [PATCH v2 2/4] Add RISC-V IOPMP support Ethan Chen via
2023-11-02 9:40 ` [PATCH v2 3/4] hw/dma: Add Andes ATCDMAC300 support Ethan Chen via
2023-11-02 9:40 ` [PATCH v2 4/4] hw/riscv/virt: Add IOPMP support Ethan Chen via
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