From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B2E4C47077 for ; Thu, 11 Jan 2024 09:09:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNr3j-0005gT-No; Thu, 11 Jan 2024 04:09:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNr3i-0005gI-Uf for qemu-devel@nongnu.org; Thu, 11 Jan 2024 04:09:06 -0500 Received: from mgamail.intel.com ([192.55.52.120]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNr3f-0004t8-5M for qemu-devel@nongnu.org; Thu, 11 Jan 2024 04:09:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704964143; x=1736500143; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=u+wzhwnjwnUJ0WCOAr9zS3iSp7euwPeQTCo/TLxYbWQ=; b=bE4k3AZKp2XHkkuPzpNxHi9lxRiZ8CJbxpN2cxHh7ywoGWBA8WwPEMVy 2xm2o/oL1vxmBZ3nVKRAjH1H85U4sG3ZUDLRu0agg2QKMhS/gO1W+s/iR wZrK5nQcAE4pzqb/RMaNL9waX9AEOKgfU5D2hJ5Jn00d8kzIgSWzVMs+Y hzLXMm4bRPglk6MKUipXUJd4aiEpwHp7lC/xH+sVZGHtmukbSvBptHUaT LLzrEdVkANw09phMN9FTvrGNhzpt3A2Izo64CLpF7YvQtAgwEzB+MwWwV ES2yFWNG2X/MBXoWKwDkv+wQJDqzzJBoS5EEfJNK7CI4+ISlKi8plXe7L g==; X-IronPort-AV: E=McAfee;i="6600,9927,10949"; a="397661160" X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="397661160" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2024 01:08:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="24566937" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.36]) by fmviesa001.fm.intel.com with ESMTP; 11 Jan 2024 01:08:50 -0800 Date: Thu, 11 Jan 2024 17:21:46 +0800 From: Zhao Liu To: Xiaoyao Li Cc: Eduardo Habkost , Marcel Apfelbaum , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Zhao Liu , Babu Moger , Yongwei Ma Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F] Message-ID: References: <20240108082727.420817-1-zhao1.liu@linux.intel.com> <20240108082727.420817-9-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: none client-ip=192.55.52.120; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -60 X-Spam_score: -6.1 X-Spam_bar: ------ X-Spam_report: (-6.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.774, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Xiaoyao, On Thu, Jan 11, 2024 at 02:04:53PM +0800, Xiaoyao Li wrote: > Date: Thu, 11 Jan 2024 14:04:53 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F] > > On 1/8/2024 4:27 PM, Zhao Liu wrote: > > From: Zhao Liu > > > > Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix > > erroneous smp_num_siblings on Intel Hybrid platforms") is able to > > handle platforms with Module level enumerated via CPUID.1F. > > > > Expose the module level in CPUID[0x1F] if the machine has more than 1 > > modules. > > > > (Tested CPU topology in CPUID[0x1F] leaf with various die/cluster > > configurations in "-smp".) > > > > Signed-off-by: Zhao Liu > > Tested-by: Babu Moger > > Tested-by: Yongwei Ma > > Acked-by: Michael S. Tsirkin > > --- > > Changes since v3: > > * New patch to expose module level in 0x1F. > > * Add Tested-by tag from Yongwei. > > --- > > target/i386/cpu.c | 12 +++++++++++- > > target/i386/cpu.h | 2 ++ > > target/i386/kvm/kvm.c | 2 +- > > 3 files changed, 14 insertions(+), 2 deletions(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index 294ca6b8947a..a2d39d2198b6 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -277,6 +277,8 @@ static uint32_t num_cpus_by_topo_level(X86CPUTopoInfo *topo_info, > > return 1; > > case CPU_TOPO_LEVEL_CORE: > > return topo_info->threads_per_core; > > + case CPU_TOPO_LEVEL_MODULE: > > + return topo_info->threads_per_core * topo_info->cores_per_module; > > case CPU_TOPO_LEVEL_DIE: > > return topo_info->threads_per_core * topo_info->cores_per_module * > > topo_info->modules_per_die; > > @@ -297,6 +299,8 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, > > return 0; > > case CPU_TOPO_LEVEL_CORE: > > return apicid_core_offset(topo_info); > > + case CPU_TOPO_LEVEL_MODULE: > > + return apicid_module_offset(topo_info); > > case CPU_TOPO_LEVEL_DIE: > > return apicid_die_offset(topo_info); > > case CPU_TOPO_LEVEL_PACKAGE: > > @@ -316,6 +320,8 @@ static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) > > return CPUID_1F_ECX_TOPO_LEVEL_SMT; > > case CPU_TOPO_LEVEL_CORE: > > return CPUID_1F_ECX_TOPO_LEVEL_CORE; > > + case CPU_TOPO_LEVEL_MODULE: > > + return CPUID_1F_ECX_TOPO_LEVEL_MODULE; > > case CPU_TOPO_LEVEL_DIE: > > return CPUID_1F_ECX_TOPO_LEVEL_DIE; > > default: > > @@ -347,6 +353,10 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, > > if (env->nr_dies > 1) { > > set_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); > > } > > + > > + if (env->nr_modules > 1) { > > + set_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap); > > + } > > } > > *ecx = count & 0xff; > > @@ -6394,7 +6404,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > break; > > case 0x1F: > > /* V2 Extended Topology Enumeration Leaf */ > > - if (topo_info.dies_per_pkg < 2) { > > + if (topo_info.modules_per_die < 2 && topo_info.dies_per_pkg < 2) { > > maybe we can come up with below function if we have env->valid_cpu_topo[] as > I suggested in patch 5. > > bool cpu_x86_has_valid_cpuid1f(CPUX86State *env) { > return env->valid_cpu_topo[2] ? true : false; > } > > ... This makes sense. > > > *eax = *ebx = *ecx = *edx = 0; > > break; > > } > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > > index eecd30bde92b..97b290e10576 100644 > > --- a/target/i386/cpu.h > > +++ b/target/i386/cpu.h > > @@ -1018,6 +1018,7 @@ enum CPUTopoLevel { > > CPU_TOPO_LEVEL_INVALID, > > CPU_TOPO_LEVEL_SMT, > > CPU_TOPO_LEVEL_CORE, > > + CPU_TOPO_LEVEL_MODULE, > > CPU_TOPO_LEVEL_DIE, > > CPU_TOPO_LEVEL_PACKAGE, > > CPU_TOPO_LEVEL_MAX, > > @@ -1032,6 +1033,7 @@ enum CPUTopoLevel { > > #define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID > > #define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT > > #define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE > > +#define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3 > > #define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 > > /* MSR Feature Bits */ > > diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c > > index 4ce80555b45c..e5ddb214cb36 100644 > > --- a/target/i386/kvm/kvm.c > > +++ b/target/i386/kvm/kvm.c > > @@ -1913,7 +1913,7 @@ int kvm_arch_init_vcpu(CPUState *cs) > > break; > > } > > case 0x1f: > > - if (env->nr_dies < 2) { > > + if (env->nr_modules < 2 && env->nr_dies < 2) { > > then cpu_x86_has_valid_cpuid1f() can be used here. > Good idae, I will also try this. Thanks, Zhao