From: fan <nifan.cxl@gmail.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org,
"Fan Ni" <fan.ni@samsung.com>, "Michael Tsirkin" <mst@redhat.com>,
"Ira Weiny" <ira.weiny@intel.com>,
"Huai-Cheng Kuo" <hchkuo@avery-design.com.tw>,
"Dave Jiang" <dave.jiang@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Davidlohr Bueso" <dave@stgolabs.net>,
"Hyeonggon Yoo" <42.hyeyoo@gmail.com>,
"Li Zhijian" <lizhijian@fujitsu.com>,
"Stefan Hajnoczi" <stefanha@gmail.com>,
linuxarm@huawei.com, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH 07/12] hw/cxl: Pass CXLComponentState to cache_mem_ops
Date: Wed, 24 Jan 2024 15:46:04 -0800 [thread overview]
Message-ID: <ZbGhPIfJgzWlnsDS@debian> (raw)
In-Reply-To: <20240124124100.8218-8-Jonathan.Cameron@huawei.com>
On Wed, Jan 24, 2024 at 12:40:55PM +0000, Jonathan Cameron wrote:
> From: Li Zhijian <lizhijian@fujitsu.com>
>
> cache_mem_ops.{read,write}() interprets opaque as
> CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs).
>
> Fortunately, cregs is the first member of cxl_cstate, so their values are
> the same.
>
> Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)")
> Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
> ---
> hw/cxl/cxl-component-utils.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> index 29d477492b..9dfde6c0b3 100644
> --- a/hw/cxl/cxl-component-utils.c
> +++ b/hw/cxl/cxl-component-utils.c
> @@ -199,7 +199,7 @@ void cxl_component_register_block_init(Object *obj,
> /* io registers controls link which we don't care about in QEMU */
> memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io",
> CXL2_COMPONENT_IO_REGION_SIZE);
> - memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
> + memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate,
> ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);
>
> memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
> --
> 2.39.2
>
next prev parent reply other threads:[~2024-01-24 23:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-24 12:40 [PATCH 00/12 qemu] CXL emulation fixes and minor cleanup Jonathan Cameron via
2024-01-24 12:40 ` [PATCH 01/12] cxl/cdat: Handle cdat table build errors Jonathan Cameron via
2024-01-24 21:04 ` fan
2024-01-24 12:40 ` [PATCH 02/12] hw/mem/cxl_type3: Drop handling of failure of g_malloc0() Jonathan Cameron via
2024-01-24 21:10 ` fan
2024-01-24 12:40 ` [PATCH 03/12] hw/pci-bridge/cxl_upstream: Drop g_malloc0() failure handling Jonathan Cameron via
2024-01-24 21:11 ` fan
2024-01-24 12:40 ` [PATCH 04/12] cxl/cdat: Fix header sum value in CDAT checksum Jonathan Cameron via
2024-01-24 12:40 ` [PATCH 05/12] hw/cxl/mbox: Remove dead code Jonathan Cameron via
2024-01-24 23:41 ` fan
2024-01-24 12:40 ` [PATCH 06/12] hw/cxl/device: read from register values in mdev_reg_read() Jonathan Cameron via
2024-01-24 12:40 ` [PATCH 07/12] hw/cxl: Pass CXLComponentState to cache_mem_ops Jonathan Cameron via
2024-01-24 23:46 ` fan [this message]
2024-01-24 12:40 ` [PATCH 08/12] hw/cxl: Pass NULL for a NULL MemoryRegionOps Jonathan Cameron via
2024-01-24 23:51 ` fan
2024-01-24 12:40 ` [PATCH 09/12] hw/mem/cxl_type3: Fix potential divide by zero reported by coverity Jonathan Cameron via
2024-01-24 23:53 ` fan
2024-01-26 11:57 ` Jonathan Cameron via
2024-01-24 12:40 ` [PATCH 10/12] tests/acpi: Allow update of DSDT.cxl Jonathan Cameron via
2024-01-24 12:40 ` [PATCH 11/12] hw/i386: Fix _STA return value for ACPI0017 Jonathan Cameron via
2024-01-24 12:41 ` [PATCH 12/12] tests/acpi: Update DSDT.cxl to reflect change _STA return value Jonathan Cameron via
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