* [PATCH v2 0/6] Add new CPU model GraniteRapids
@ 2023-07-06 5:49 Tao Su
2023-07-06 5:49 ` [PATCH v2 1/6] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Tao Su @ 2023-07-06 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen, tao1.su
This patch series mainly updates SapphireRapids CPU model and adds new
CPU model GraniteRapids.
Bit 13 (ARCH_CAP_SBDR_SSDP_NO), bit 14 (ARCH_CAP_FBSDP_NO) and bit 15
(ARCH_CAP_PSDP_NO) of MSR_IA32_ARCH_CAPABILITIES are enumerated starting
from SapphireRapids, which are missed in current SapphireRapids CPU model,
so add a new version for SapphireRapids CPU model to expose these bits.
GraniteRapids is Intel's successor to EmeraldRapids, an Intel 3 process
microarchitecture for enthusiasts and servers, which adds new features
based on SapphireRapids. The new features can be found in [1].
---
Changelog:
v2:
- Drop the same part of patch[2]
- Drop EmeraldRapids CPU model
- Change the commit messages to make these clear
v1: https://lore.kernel.org/all/20230616032311.19137-1-tao1.su@linux.intel.com/
[1] https://cdrdv2.intel.com/v1/dl/getContent/671368
[2]
https://lore.kernel.org/all/63d85cc76d4cdc51e6c732478b81d8f13be11e5a.1687551881.git.pawan.kumar.gupta@linux.intel.com/
Lei Wang (1):
target/i386: Add few security fix bits in ARCH_CAPABILITIES into
SapphireRapids CPU model
Tao Su (5):
target/i386: Add FEAT_7_1_EDX to adjust feature level
target/i386: Add support for MCDT_NO in CPUID enumeration
target/i386: Allow MCDT_NO if host supports
target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
target/i386: Add new CPU model GraniteRapids
target/i386/cpu.c | 172 ++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 8 ++
target/i386/kvm/kvm.c | 4 +
3 files changed, 184 insertions(+)
base-commit: 2a6ae69154542caa91dd17c40fd3f5ffbec300de
--
2.34.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/6] target/i386: Add FEAT_7_1_EDX to adjust feature level
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
@ 2023-07-06 5:49 ` Tao Su
2023-07-06 5:49 ` [PATCH v2 2/6] target/i386: Add support for MCDT_NO in CPUID enumeration Tao Su
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Tao Su @ 2023-07-06 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen, tao1.su
Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
non-zero. Such as starting a VM on GraniteRapids using '-cpu host',
we can see two leafs CPUID_7_0 and CPUID_7_1 in VM, because both
CPUID_7_1_EAX and CPUID_7_1_EDX have non-zero value, but if minus all
FEAT_7_1_EAX features using
'-cpu host,-avx-vnni,-avx512-bf16,-fzrm,-fsrs,-fsrc,-amx-fp16', we can't
get CPUID_7_1 leaf even though CPUID_7_1_EDX has non-zero value.
So it is necessary to update cpuid_level_func7 by CPUID_7_1_EDX, otherwise
guest may report wrong maximum number sub-leaves in leaf 07H.
Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
enumeration")
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b5688cabb4..952744af97 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6880,6 +6880,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
+ x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/6] target/i386: Add support for MCDT_NO in CPUID enumeration
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
2023-07-06 5:49 ` [PATCH v2 1/6] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
@ 2023-07-06 5:49 ` Tao Su
2023-07-06 5:49 ` [PATCH v2 3/6] target/i386: Allow MCDT_NO if host supports Tao Su
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Tao Su @ 2023-07-06 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen, tao1.su
CPUID.(EAX=7,ECX=2):EDX[bit 5] enumerates MCDT_NO. Processors enumerate
this bit as 1 do not exhibit MXCSR Configuration Dependent Timing (MCDT)
behavior and do not need to be mitigated to avoid data-dependent behavior
for certain instructions.
Since MCDT_NO is in a new sub-leaf, add a new CPUID feature word
FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/cpu.c | 26 ++++++++++++++++++++++++++
target/i386/cpu.h | 4 ++++
2 files changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 952744af97..852c45b965 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -739,6 +739,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
CPUID_7_1_EAX_FSRC)
#define TCG_7_1_EDX_FEATURES 0
+#define TCG_7_2_EDX_FEATURES 0
#define TCG_APM_FEATURES 0
#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
@@ -993,6 +994,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_7_1_EDX_FEATURES,
},
+ [FEAT_7_2_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, "mcdt-no", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 2,
+ .reg = R_EDX,
+ },
+ .tcg_features = TCG_7_2_EDX_FEATURES,
+ },
[FEAT_8000_0007_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
@@ -6017,6 +6037,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*edx = env->features[FEAT_7_1_EDX];
*ebx = 0;
*ecx = 0;
+ } else if (count == 2) {
+ *edx = env->features[FEAT_7_2_EDX];
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
} else {
*eax = 0;
*ebx = 0;
@@ -6881,6 +6906,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
+ x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c9b0d2ebc..c196b0a482 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -628,6 +628,7 @@ typedef enum FeatureWord {
FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */
FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
+ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
FEATURE_WORDS,
} FeatureWord;
@@ -932,6 +933,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
/* PREFETCHIT0/1 Instructions */
#define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
+/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
+#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
+
/* XFD Extend Feature Disabled */
#define CPUID_D_1_EAX_XFD (1U << 4)
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/6] target/i386: Allow MCDT_NO if host supports
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
2023-07-06 5:49 ` [PATCH v2 1/6] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
2023-07-06 5:49 ` [PATCH v2 2/6] target/i386: Add support for MCDT_NO in CPUID enumeration Tao Su
@ 2023-07-06 5:49 ` Tao Su
2023-07-06 5:49 ` [PATCH v2 4/6] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Tao Su
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Tao Su @ 2023-07-06 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen, tao1.su
MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/kvm/kvm.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index de531842f6..ebfaf3d24c 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -432,6 +432,10 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
uint32_t eax;
host_cpuid(7, 1, &eax, &unused, &unused, &unused);
ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
+ } else if (function == 7 && index == 2 && reg == R_EDX) {
+ uint32_t edx;
+ host_cpuid(7, 2, &unused, &unused, &unused, &edx);
+ ret |= edx & CPUID_7_2_EDX_MCDT_NO;
} else if (function == 0xd && index == 0 &&
(reg == R_EAX || reg == R_EDX)) {
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/6] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
` (2 preceding siblings ...)
2023-07-06 5:49 ` [PATCH v2 3/6] target/i386: Allow MCDT_NO if host supports Tao Su
@ 2023-07-06 5:49 ` Tao Su
2023-07-06 5:49 ` [PATCH v2 5/6] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Tao Su
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Tao Su @ 2023-07-06 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen, tao1.su
Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions.
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
target/i386/cpu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c196b0a482..e0771a1043 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1022,7 +1022,11 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
#define MSR_ARCH_CAP_TAA_NO (1U << 8)
+#define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13)
+#define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
+#define MSR_ARCH_CAP_PSDP_NO (1U << 15)
#define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
+#define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 5/6] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
` (3 preceding siblings ...)
2023-07-06 5:49 ` [PATCH v2 4/6] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Tao Su
@ 2023-07-06 5:49 ` Tao Su
2023-07-06 5:49 ` [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids Tao Su
2023-07-07 10:52 ` [PATCH v2 0/6] " Paolo Bonzini
6 siblings, 0 replies; 13+ messages in thread
From: Tao Su @ 2023-07-06 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen, tao1.su
From: Lei Wang <lei4.wang@intel.com>
SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES
enabled, which are related to some security fixes.
Add version 2 of SapphireRapids CPU model with those bits enabled also.
Signed-off-by: Lei Wang <lei4.wang@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
target/i386/cpu.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 852c45b965..ec229072e7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3944,8 +3944,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Intel Xeon Processor (SapphireRapids)",
.versions = (X86CPUVersionDefinition[]) {
{ .version = 1 },
- { /* end of list */ },
- },
+ {
+ .version = 2,
+ .props = (PropValue[]) {
+ { "sbdr-ssdp-no", "on" },
+ { "fbsdp-no", "on" },
+ { "psdp-no", "on" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Denverton",
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
` (4 preceding siblings ...)
2023-07-06 5:49 ` [PATCH v2 5/6] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Tao Su
@ 2023-07-06 5:49 ` Tao Su
2024-01-30 10:14 ` Igor Mammedov
2023-07-07 10:52 ` [PATCH v2 0/6] " Paolo Bonzini
6 siblings, 1 reply; 13+ messages in thread
From: Tao Su @ 2023-07-06 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen, tao1.su
The GraniteRapids CPU model mainly adds the following new features
based on SapphireRapids:
- PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
And adds the following security fix for corresponding vulnerabilities:
- MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
- SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
- FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
- PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
- PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/cpu.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ec229072e7..97ad229d8b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3956,6 +3956,142 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .name = "GraniteRapids",
+ .level = 0x20,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 173,
+ .stepping = 0,
+ /*
+ * please keep the ascending order so that we can have a clear view of
+ * bit position of each feature.
+ */
+ .features[FEAT_1_EDX] =
+ CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
+ CPUID_SSE | CPUID_SSE2,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
+ CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+ CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
+ CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
+ CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_8000_0008_EBX] =
+ CPUID_8000_0008_EBX_WBNOINVD,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
+ CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
+ CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
+ CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
+ CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
+ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
+ CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
+ CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
+ CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
+ .features[FEAT_7_0_EDX] =
+ CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
+ CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
+ CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
+ CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
+ CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+ .features[FEAT_ARCH_CAPABILITIES] =
+ MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
+ MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
+ MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
+ MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
+ MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .features[FEAT_7_1_EAX] =
+ CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
+ CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
+ CPUID_7_1_EAX_AMX_FP16,
+ .features[FEAT_7_1_EDX] =
+ CPUID_7_1_EDX_PREFETCHITI,
+ .features[FEAT_7_2_EDX] =
+ CPUID_7_2_EDX_MCDT_NO,
+ .features[FEAT_VMX_BASIC] =
+ MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+ .features[FEAT_VMX_ENTRY_CTLS] =
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+ VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+ .features[FEAT_VMX_EPT_VPID_CAPS] =
+ MSR_VMX_EPT_EXECONLY |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
+ MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+ MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
+ MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+ .features[FEAT_VMX_EXIT_CTLS] =
+ VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+ VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+ .features[FEAT_VMX_MISC] =
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+ MSR_VMX_MISC_VMWRITE_VMEXIT,
+ .features[FEAT_VMX_PINBASED_CTLS] =
+ VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+ VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+ VMX_PIN_BASED_POSTED_INTR,
+ .features[FEAT_VMX_PROCBASED_CTLS] =
+ VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
+ VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
+ VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
+ VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
+ VMX_CPU_BASED_PAUSE_EXITING |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+ .features[FEAT_VMX_SECONDARY_CTLS] =
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+ VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+ VMX_SECONDARY_EXEC_RDTSCP |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
+ VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING |
+ VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
+ VMX_SECONDARY_EXEC_XSAVES,
+ .features[FEAT_VMX_VMFUNC] =
+ MSR_VMX_VMFUNC_EPT_SWITCHING,
+ .xlevel = 0x80000008,
+ .model_id = "Intel Xeon Processor (GraniteRapids)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ { /* end of list */ },
+ },
+ },
{
.name = "Denverton",
.level = 21,
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/6] Add new CPU model GraniteRapids
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
` (5 preceding siblings ...)
2023-07-06 5:49 ` [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids Tao Su
@ 2023-07-07 10:52 ` Paolo Bonzini
2023-07-07 12:37 ` Tao Su
6 siblings, 1 reply; 13+ messages in thread
From: Paolo Bonzini @ 2023-07-07 10:52 UTC (permalink / raw)
To: Tao Su; +Cc: qemu-devel, pbonzini, imammedo, xiaoyao.li, lei4.wang, qian.wen
Queued, thanks.
Paolo
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/6] Add new CPU model GraniteRapids
2023-07-07 10:52 ` [PATCH v2 0/6] " Paolo Bonzini
@ 2023-07-07 12:37 ` Tao Su
0 siblings, 0 replies; 13+ messages in thread
From: Tao Su @ 2023-07-07 12:37 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, imammedo, xiaoyao.li, lei4.wang, qian.wen
On Fri, Jul 07, 2023 at 12:52:37PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
Paolo, thanks!
>
> Paolo
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids
2023-07-06 5:49 ` [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids Tao Su
@ 2024-01-30 10:14 ` Igor Mammedov
2024-01-30 13:34 ` Tao Su
0 siblings, 1 reply; 13+ messages in thread
From: Igor Mammedov @ 2024-01-30 10:14 UTC (permalink / raw)
To: Tao Su; +Cc: qemu-devel, pbonzini, xiaoyao.li, lei4.wang, qian.wen
On Thu, 6 Jul 2023 13:49:49 +0800
Tao Su <tao1.su@linux.intel.com> wrote:
> The GraniteRapids CPU model mainly adds the following new features
> based on SapphireRapids:
> - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
it seems the list/definition is not complete, see
https://lore.kernel.org/kvm/20221125125845.1182922-1-jiaxi.chen@linux.intel.com/
and those feature bits were merged into QEMU earlier (a9ce107fd0f..d1a11115143)
were they omited intentionaly?
> And adds the following security fix for corresponding vulnerabilities:
> - MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
> - SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
> - FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
> - PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
> - PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
>
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> Tested-by: Xuelian Guo <xuelian.guo@intel.com>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> target/i386/cpu.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 136 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index ec229072e7..97ad229d8b 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3956,6 +3956,142 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> { /* end of list */ }
> }
> },
> + {
> + .name = "GraniteRapids",
> + .level = 0x20,
> + .vendor = CPUID_VENDOR_INTEL,
> + .family = 6,
> + .model = 173,
> + .stepping = 0,
> + /*
> + * please keep the ascending order so that we can have a clear view of
> + * bit position of each feature.
> + */
> + .features[FEAT_1_EDX] =
> + CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
> + CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
> + CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
> + CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
> + CPUID_SSE | CPUID_SSE2,
> + .features[FEAT_1_ECX] =
> + CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
> + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
> + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
> + CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
> + CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
> + .features[FEAT_8000_0001_EDX] =
> + CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
> + CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
> + .features[FEAT_8000_0001_ECX] =
> + CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
> + .features[FEAT_8000_0008_EBX] =
> + CPUID_8000_0008_EBX_WBNOINVD,
> + .features[FEAT_7_0_EBX] =
> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
> + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> + CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
> + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
> + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
> + CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
> + CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
> + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
> + .features[FEAT_7_0_ECX] =
> + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> + CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
> + CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
> + CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
> + CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
> + CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
> + .features[FEAT_7_0_EDX] =
> + CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
> + CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
> + CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
> + CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
> + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
> + .features[FEAT_ARCH_CAPABILITIES] =
> + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
> + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
> + MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
> + MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
> + MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
> + .features[FEAT_XSAVE] =
> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
> + .features[FEAT_6_EAX] =
> + CPUID_6_EAX_ARAT,
> + .features[FEAT_7_1_EAX] =
> + CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
> + CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
> + CPUID_7_1_EAX_AMX_FP16,
> + .features[FEAT_7_1_EDX] =
> + CPUID_7_1_EDX_PREFETCHITI,
> + .features[FEAT_7_2_EDX] =
> + CPUID_7_2_EDX_MCDT_NO,
> + .features[FEAT_VMX_BASIC] =
> + MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
> + .features[FEAT_VMX_ENTRY_CTLS] =
> + VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
> + VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
> + VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
> + .features[FEAT_VMX_EPT_VPID_CAPS] =
> + MSR_VMX_EPT_EXECONLY |
> + MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
> + MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
> + MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
> + MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
> + MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
> + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
> + MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
> + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
> + .features[FEAT_VMX_EXIT_CTLS] =
> + VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
> + VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> + VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> + VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> + .features[FEAT_VMX_MISC] =
> + MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> + MSR_VMX_MISC_VMWRITE_VMEXIT,
> + .features[FEAT_VMX_PINBASED_CTLS] =
> + VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
> + VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
> + VMX_PIN_BASED_POSTED_INTR,
> + .features[FEAT_VMX_PROCBASED_CTLS] =
> + VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
> + VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
> + VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
> + VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
> + VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
> + VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
> + VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
> + VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
> + VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
> + VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
> + VMX_CPU_BASED_PAUSE_EXITING |
> + VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
> + .features[FEAT_VMX_SECONDARY_CTLS] =
> + VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
> + VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
> + VMX_SECONDARY_EXEC_RDTSCP |
> + VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
> + VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
> + VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
> + VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
> + VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
> + VMX_SECONDARY_EXEC_RDRAND_EXITING |
> + VMX_SECONDARY_EXEC_ENABLE_INVPCID |
> + VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
> + VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
> + VMX_SECONDARY_EXEC_XSAVES,
> + .features[FEAT_VMX_VMFUNC] =
> + MSR_VMX_VMFUNC_EPT_SWITCHING,
> + .xlevel = 0x80000008,
> + .model_id = "Intel Xeon Processor (GraniteRapids)",
> + .versions = (X86CPUVersionDefinition[]) {
> + { .version = 1 },
> + { /* end of list */ },
> + },
> + },
> {
> .name = "Denverton",
> .level = 21,
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids
2024-01-30 10:14 ` Igor Mammedov
@ 2024-01-30 13:34 ` Tao Su
2024-01-31 12:34 ` Igor Mammedov
0 siblings, 1 reply; 13+ messages in thread
From: Tao Su @ 2024-01-30 13:34 UTC (permalink / raw)
To: Igor Mammedov; +Cc: qemu-devel, pbonzini, xiaoyao.li, lei4.wang, qian.wen
On Tue, Jan 30, 2024 at 11:14:59AM +0100, Igor Mammedov wrote:
> On Thu, 6 Jul 2023 13:49:49 +0800
> Tao Su <tao1.su@linux.intel.com> wrote:
>
> > The GraniteRapids CPU model mainly adds the following new features
> > based on SapphireRapids:
> > - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> > - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
>
> it seems the list/definition is not complete, see
> https://lore.kernel.org/kvm/20221125125845.1182922-1-jiaxi.chen@linux.intel.com/
> and those feature bits were merged into QEMU earlier (a9ce107fd0f..d1a11115143)
>
> were they omited intentionaly?
>
No, Jiaxi’s patch series includes new feature bits of both Granite Rapids(GNR)
and Sierra Forest(SRF).
GNR contains:
PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
SRF contains:
CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
AVX-VNNI-INT8 CPUID.(EAX=7,ECX=1):EDX[bit 4]
AVX-NE-CONVERT CPUID.(EAX=7,ECX=1):EDX[bit 5]
What new platforms support the new features can be found in Table 1-2 of ISE[1].
And the SRF CPU model we submitted[2] contains the four feature bits supported above.
[1] https://cdrdv2.intel.com/v1/dl/getContent/671368
[2] https://lore.kernel.org/all/20231206131923.1192066-1-tao1.su@linux.intel.com/
Thanks,
Tao
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids
2024-01-30 13:34 ` Tao Su
@ 2024-01-31 12:34 ` Igor Mammedov
2024-01-31 13:01 ` Tao Su
0 siblings, 1 reply; 13+ messages in thread
From: Igor Mammedov @ 2024-01-31 12:34 UTC (permalink / raw)
To: Tao Su; +Cc: qemu-devel, pbonzini, xiaoyao.li, lei4.wang, qian.wen
On Tue, 30 Jan 2024 21:34:36 +0800
Tao Su <tao1.su@linux.intel.com> wrote:
> On Tue, Jan 30, 2024 at 11:14:59AM +0100, Igor Mammedov wrote:
> > On Thu, 6 Jul 2023 13:49:49 +0800
> > Tao Su <tao1.su@linux.intel.com> wrote:
> >
> > > The GraniteRapids CPU model mainly adds the following new features
> > > based on SapphireRapids:
> > > - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> > > - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> >
> > it seems the list/definition is not complete, see
> > https://lore.kernel.org/kvm/20221125125845.1182922-1-jiaxi.chen@linux.intel.com/
> > and those feature bits were merged into QEMU earlier (a9ce107fd0f..d1a11115143)
> >
> > were they omited intentionaly?
> >
>
> No, Jiaxi’s patch series includes new feature bits of both Granite Rapids(GNR)
> and Sierra Forest(SRF).
>
> GNR contains:
> PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
>
> SRF contains:
> CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
> AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
> AVX-VNNI-INT8 CPUID.(EAX=7,ECX=1):EDX[bit 4]
> AVX-NE-CONVERT CPUID.(EAX=7,ECX=1):EDX[bit 5]
> What new platforms support the new features can be found in Table 1-2 of ISE[1].
> And the SRF CPU model we submitted[2] contains the four feature bits supported above.
Thanks,
for future patches:
this kind of info should be part of commit message incl.
spec/doc title/revision it's coming from with a specific
chapter/table also mentioned. This way whoever reads it
later won't have to ask or spend time for searching where
it comes from.
And maybe also have a comment close to new code,
aka like we do for ACPI patches.
> [1] https://cdrdv2.intel.com/v1/dl/getContent/671368
> [2] https://lore.kernel.org/all/20231206131923.1192066-1-tao1.su@linux.intel.com/
>
> Thanks,
> Tao
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids
2024-01-31 12:34 ` Igor Mammedov
@ 2024-01-31 13:01 ` Tao Su
0 siblings, 0 replies; 13+ messages in thread
From: Tao Su @ 2024-01-31 13:01 UTC (permalink / raw)
To: Igor Mammedov; +Cc: qemu-devel, pbonzini, xiaoyao.li, lei4.wang, qian.wen
On Wed, Jan 31, 2024 at 01:34:31PM +0100, Igor Mammedov wrote:
> On Tue, 30 Jan 2024 21:34:36 +0800
> Tao Su <tao1.su@linux.intel.com> wrote:
>
> > On Tue, Jan 30, 2024 at 11:14:59AM +0100, Igor Mammedov wrote:
> > > On Thu, 6 Jul 2023 13:49:49 +0800
> > > Tao Su <tao1.su@linux.intel.com> wrote:
> > >
> > > > The GraniteRapids CPU model mainly adds the following new features
> > > > based on SapphireRapids:
> > > > - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> > > > - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> > >
> > > it seems the list/definition is not complete, see
> > > https://lore.kernel.org/kvm/20221125125845.1182922-1-jiaxi.chen@linux.intel.com/
> > > and those feature bits were merged into QEMU earlier (a9ce107fd0f..d1a11115143)
> > >
> > > were they omited intentionaly?
> > >
> >
> > No, Jiaxi’s patch series includes new feature bits of both Granite Rapids(GNR)
> > and Sierra Forest(SRF).
> >
> > GNR contains:
> > PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> > AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> >
> > SRF contains:
> > CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
> > AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
> > AVX-VNNI-INT8 CPUID.(EAX=7,ECX=1):EDX[bit 4]
> > AVX-NE-CONVERT CPUID.(EAX=7,ECX=1):EDX[bit 5]
>
> > What new platforms support the new features can be found in Table 1-2 of ISE[1].
> > And the SRF CPU model we submitted[2] contains the four feature bits supported above.
> Thanks,
>
> for future patches:
> this kind of info should be part of commit message incl.
> spec/doc title/revision it's coming from with a specific
> chapter/table also mentioned. This way whoever reads it
> later won't have to ask or spend time for searching where
> it comes from.
>
> And maybe also have a comment close to new code,
> aka like we do for ACPI patches.
Got it, thanks for the suggestion! This is really useful, I will do.
Thanks,
Tao
>
> > [1] https://cdrdv2.intel.com/v1/dl/getContent/671368
> > [2] https://lore.kernel.org/all/20231206131923.1192066-1-tao1.su@linux.intel.com/
> >
> > Thanks,
> > Tao
> >
>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-01-31 13:05 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-06 5:49 [PATCH v2 0/6] Add new CPU model GraniteRapids Tao Su
2023-07-06 5:49 ` [PATCH v2 1/6] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
2023-07-06 5:49 ` [PATCH v2 2/6] target/i386: Add support for MCDT_NO in CPUID enumeration Tao Su
2023-07-06 5:49 ` [PATCH v2 3/6] target/i386: Allow MCDT_NO if host supports Tao Su
2023-07-06 5:49 ` [PATCH v2 4/6] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Tao Su
2023-07-06 5:49 ` [PATCH v2 5/6] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Tao Su
2023-07-06 5:49 ` [PATCH v2 6/6] target/i386: Add new CPU model GraniteRapids Tao Su
2024-01-30 10:14 ` Igor Mammedov
2024-01-30 13:34 ` Tao Su
2024-01-31 12:34 ` Igor Mammedov
2024-01-31 13:01 ` Tao Su
2023-07-07 10:52 ` [PATCH v2 0/6] " Paolo Bonzini
2023-07-07 12:37 ` Tao Su
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