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[34.140.83.185]) by smtp.gmail.com with ESMTPSA id v5-20020a5d59c5000000b0033b8305ffe2sm4605707wry.87.2024.02.13.02.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Feb 2024 02:12:04 -0800 (PST) Date: Tue, 13 Feb 2024 10:12:01 +0000 From: Mostafa Saleh To: Luc Michel Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Eric Auger , Peter Maydell , Francisco Iglesias Subject: Re: [PATCH v2] hw/arm/smmuv3: add support for stage 1 access fault Message-ID: References: <20240213082211.3330400-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240213082211.3330400-1-luc.michel@amd.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=smostafa@google.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, FSL_HELO_FAKE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Luc, On Tue, Feb 13, 2024 at 09:22:11AM +0100, Luc Michel wrote: > An access fault is raised when the Access Flag is not set in the > looked-up PTE and the AFFD field is not set in the corresponding context > descriptor. This was already implemented for stage 2. Implement it for > stage 1 as well. > I noticed the same thing when writing PTW for stage-2, I don’t think there is any reason this is not supported for stage-1, as SMMUv3.0-HTTU* are not supported any SW broken will be due to an existing SW bug. Reviewed-by: Mostafa Saleh Tested-by: Mostafa Saleh > Signed-off-by: Luc Michel > --- > > v2: drop erroneous submodule modification > > --- > > hw/arm/smmuv3-internal.h | 1 + > include/hw/arm/smmu-common.h | 1 + > hw/arm/smmu-common.c | 10 ++++++++++ > hw/arm/smmuv3.c | 1 + > 4 files changed, 13 insertions(+) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index e987bc4686b..e4dd11e1e62 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -622,10 +622,11 @@ static inline int pa_range(STE *ste) > #define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6) > #define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2) > #define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1) > #define CD_ENDI(x) extract32((x)->word[0], 15, 1) > #define CD_IPS(x) extract32((x)->word[1], 0 , 3) > +#define CD_AFFD(x) extract32((x)->word[1], 3 , 1) > #define CD_TBI(x) extract32((x)->word[1], 6 , 2) > #define CD_HD(x) extract32((x)->word[1], 10 , 1) > #define CD_HA(x) extract32((x)->word[1], 11 , 1) > #define CD_S(x) extract32((x)->word[1], 12, 1) > #define CD_R(x) extract32((x)->word[1], 13, 1) > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index fd8d772da11..5ec2e6c1a43 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -90,10 +90,11 @@ typedef struct SMMUTransCfg { > /* Shared fields between stage-1 and stage-2. */ > int stage; /* translation stage */ > bool disabled; /* smmu is disabled */ > bool bypassed; /* translation is bypassed */ > bool aborted; /* translation is aborted */ > + bool affd; /* AF fault disable */ > uint32_t iotlb_hits; /* counts IOTLB hits */ > uint32_t iotlb_misses; /* counts IOTLB misses*/ > /* Used by stage-1 only. */ > bool aa64; /* arch64 or aarch32 translation table */ > bool record_faults; /* record fault events */ > diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c > index 9a8ac45431a..09ff72e55f5 100644 > --- a/hw/arm/smmu-common.c > +++ b/hw/arm/smmu-common.c > @@ -362,10 +362,20 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, > &block_size); > trace_smmu_ptw_block_pte(stage, level, baseaddr, > pte_addr, pte, iova, gpa, > block_size >> 20); > } > + > + /* > + * If AFFD and PTE.AF are 0 => fault. (5.4. Context Descriptor) > + * An Access fault takes priority over a Permission fault. > + */ > + if (!PTE_AF(pte) && !cfg->affd) { > + info->type = SMMU_PTW_ERR_ACCESS; > + goto error; > + } > + > ap = PTE_AP(pte); > if (is_permission_fault(ap, perm)) { > info->type = SMMU_PTW_ERR_PERMISSION; > goto error; > } > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 68eeef3e1d4..c416b8c0030 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -682,10 +682,11 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) > > cfg->oas = oas2bits(CD_IPS(cd)); > cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); > cfg->tbi = CD_TBI(cd); > cfg->asid = CD_ASID(cd); > + cfg->affd = CD_AFFD(cd); > > trace_smmuv3_decode_cd(cfg->oas); > > /* decode data dependent on TT */ > for (i = 0; i <= 1; i++) { > -- > 2.39.2 Thanks, Mostafa