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d="scan'208";a="936985813" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.36]) by fmsmga001.fm.intel.com with ESMTP; 22 Feb 2024 18:58:59 -0800 Date: Fri, 23 Feb 2024 11:12:40 +0800 From: Zhao Liu To: Binbin Wu Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, pbonzini@redhat.com, xiaoyao.li@intel.com, chao.gao@intel.com, robert.hu@linux.intel.com Subject: Re: [PATCH v4 1/2] target/i386: add support for LAM in CPUID enumeration Message-ID: References: <20240112060042.19925-1-binbin.wu@linux.intel.com> <20240112060042.19925-2-binbin.wu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240112060042.19925-2-binbin.wu@linux.intel.com> Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.002, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Jan 12, 2024 at 02:00:41PM +0800, Binbin Wu wrote: > Date: Fri, 12 Jan 2024 14:00:41 +0800 > From: Binbin Wu > Subject: [PATCH v4 1/2] target/i386: add support for LAM in CPUID > enumeration > X-Mailer: git-send-email 2.25.1 > > From: Robert Hoo > > Linear Address Masking (LAM) is a new Intel CPU feature, which allows > software to use of the untranslated address bits for metadata. > > The bit definition: > CPUID.(EAX=7,ECX=1):EAX[26] > > Add CPUID definition for LAM. > > Note LAM feature is not supported for TCG of target-i386, LAM CPIUD bit > will not be added to TCG_7_1_EAX_FEATURES. > > More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING(LAM)" > https://cdrdv2.intel.com/v1/dl/getContent/671368 > > Signed-off-by: Robert Hoo > Co-developed-by: Binbin Wu > Signed-off-by: Binbin Wu > Tested-by: Xuelian Guo > Reviewed-by: Xiaoyao Li > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Zhao Liu > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 2524881ce2..fc862dfeb1 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -967,7 +967,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > "fsrc", NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > NULL, "amx-fp16", NULL, "avx-ifma", > - NULL, NULL, NULL, NULL, > + NULL, NULL, "lam", NULL, > NULL, NULL, NULL, NULL, > }, > .cpuid = { > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 7f0786e8b9..18ea755644 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -925,6 +925,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, > #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) > /* Support for VPMADD52[H,L]UQ */ > #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) > +/* Linear Address Masking */ > +#define CPUID_7_1_EAX_LAM (1U << 26) > > /* Support for VPDPB[SU,UU,SS]D[,S] */ > #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) > -- > 2.25.1 > >