From: Zhao Liu <zhao1.liu@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, mcb30@ipxe.org
Subject: Re: [PATCH v2 1/7] target/i386: mask high bits of CR3 in 32-bit mode
Date: Mon, 26 Feb 2024 16:04:31 +0800 [thread overview]
Message-ID: <ZdxGD1NhtoUljLSm@intel.com> (raw)
In-Reply-To: <20240223130948.237186-2-pbonzini@redhat.com>
On Fri, Feb 23, 2024 at 02:09:42PM +0100, Paolo Bonzini wrote:
> Date: Fri, 23 Feb 2024 14:09:42 +0100
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH v2 1/7] target/i386: mask high bits of CR3 in 32-bit mode
> X-Mailer: git-send-email 2.43.0
>
> CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
> paging or PAE paging). Do this in mmu_translate() to remove
> the last case where get_physical_address() meaningfully drops
> the high bits of the address.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2022-10-18)
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/sysemu/excp_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
>
> diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
> index 5b86f439add..11126c860d4 100644
> --- a/target/i386/tcg/sysemu/excp_helper.c
> +++ b/target/i386/tcg/sysemu/excp_helper.c
> @@ -238,7 +238,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
> /*
> * Page table level 3
> */
> - pte_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20_mask;
> + pte_addr = ((in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18)) & a20_mask;
> if (!ptw_translate(&pte_trans, pte_addr)) {
> return false;
> }
> @@ -306,7 +306,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
> /*
> * Page table level 2
> */
> - pte_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
> + pte_addr = ((in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc)) & a20_mask;
> if (!ptw_translate(&pte_trans, pte_addr)) {
> return false;
> }
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2024-02-26 7:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 13:09 [PATCH v2 0/7] target/i386: Fix physical address masking bugs Paolo Bonzini
2024-02-23 13:09 ` [PATCH v2 1/7] target/i386: mask high bits of CR3 in 32-bit mode Paolo Bonzini
2024-02-26 8:04 ` Zhao Liu [this message]
2024-02-23 13:09 ` [PATCH v2 2/7] target/i386: check validity of VMCB addresses Paolo Bonzini
2024-02-23 13:09 ` [PATCH v2 3/7] target/i386: introduce function to query MMU indices Paolo Bonzini
2024-02-26 8:05 ` Zhao Liu
2024-02-23 13:09 ` [PATCH v2 4/7] target/i386: use separate MMU indexes for 32-bit accesses Paolo Bonzini
2024-02-26 8:36 ` Zhao Liu
2024-02-26 9:55 ` Paolo Bonzini
2024-02-26 12:59 ` Zhao Liu
2024-02-23 13:09 ` [PATCH v2 5/7] target/i386: Fix physical address truncation Paolo Bonzini
2024-02-26 8:31 ` Zhao Liu
2024-02-23 13:09 ` [PATCH v2 6/7] target/i386: remove unnecessary/wrong application of the A20 mask Paolo Bonzini
2024-02-23 13:09 ` [PATCH v2 7/7] target/i386: leave the A20 bit set in the final NPT walk Paolo Bonzini
2024-02-23 17:57 ` [PATCH v2 0/7] target/i386: Fix physical address masking bugs Michael Brown
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