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From: Zhao Liu <zhao1.liu@linux.intel.com>
To: JeeHeng Sia <jeeheng.sia@starfivetech.com>
Cc: "Daniel P . Berrang�" <berrange@redhat.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Philippe Mathieu-Daud�" <philmd@linaro.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eric Blake" <eblake@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Marcelo Tosatti" <mtosatti@redhat.com>,
	"Alex Benn�e" <alex.bennee@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	"Zhenyu Wang" <zhenyu.z.wang@intel.com>,
	"Dapeng Mi" <dapeng1.mi@linux.intel.com>,
	"Yongwei Ma" <yongwei.ma@intel.com>,
	"Zhao Liu" <zhao1.liu@intel.com>
Subject: Re: [RFC 4/8] hw/core: Add cache topology options in -smp
Date: Thu, 29 Feb 2024 15:04:42 +0800	[thread overview]
Message-ID: <ZeAsijVdx6DO+1pP@intel.com> (raw)
In-Reply-To: <BJSPR01MB05618A7D409C2DE3E408345C9C58A@BJSPR01MB0561.CHNPR01.prod.partner.outlook.cn>

Hi JeeHeng,

> > diff --git a/hw/core/machine.c b/hw/core/machine.c
> > index 426f71770a84..cb5173927b0d 100644
> > --- a/hw/core/machine.c
> > +++ b/hw/core/machine.c
> > @@ -886,6 +886,10 @@ static void machine_get_smp(Object *obj, Visitor *v, const char *name,
> >          .has_cores = true, .cores = ms->smp.cores,
> >          .has_threads = true, .threads = ms->smp.threads,
> >          .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
> > +        .l1d_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1d)),
> > +        .l1i_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1i)),
> > +        .l2_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l2)),
> > +        .l3_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l3)),
>
> Let's standardize the code by adding the 'has_' prefix.

SMPConfiguration is automatically generated in the compilation, and its
prototype is defined in qapi/machine.json like the following code:


> > diff --git a/qapi/machine.json b/qapi/machine.json
> > index d0e7f1f615f3..0a923ac38803 100644
> > --- a/qapi/machine.json
> > +++ b/qapi/machine.json
> > @@ -1650,6 +1650,14 @@
> >  #
> >  # @threads: number of threads per core
> >  #
> > +# @l1d-cache: topology hierarchy of L1 data cache (since 9.0)
> > +#
> > +# @l1i-cache: topology hierarchy of L1 instruction cache (since 9.0)
> > +#
> > +# @l2-cache: topology hierarchy of L2 unified cache (since 9.0)
> > +#
> > +# @l3-cache: topology hierarchy of L3 unified cache (since 9.0)
> > +#
> >  # Since: 6.1
> >  ##
> >  { 'struct': 'SMPConfiguration', 'data': {
> > @@ -1662,7 +1670,11 @@
> >       '*modules': 'int',
> >       '*cores': 'int',
> >       '*threads': 'int',
> > -     '*maxcpus': 'int' } }
> > +     '*maxcpus': 'int',
> > +     '*l1d-cache': 'str',
> > +     '*l1i-cache': 'str',
> > +     '*l2-cache': 'str',
> > +     '*l3-cache': 'str' } }
> >

The gnerated complete structure is (will in build/qapi/qapi-types-machine.h):

struct SMPConfiguration {
    bool has_cpus;
    int64_t cpus;
    bool has_drawers;
    int64_t drawers;
    bool has_books;
    int64_t books;
    bool has_sockets;
    int64_t sockets;
    bool has_dies;
    int64_t dies;
    bool has_clusters;
    int64_t clusters;
    bool has_modules;
    int64_t modules;
    bool has_cores;
    int64_t cores;
    bool has_threads;
    int64_t threads;
    bool has_maxcpus;
    int64_t maxcpus;
    char *l1d_cache;
    char *l1i_cache;
    char *l2_cache;
    char *l3_cache;
};

The int member defined in qapi/machine.json will get their corresponding
status fields as has_* to indicate if user sets those int fields.

For str type, the status field is not needed since NULL is enough to
indicate no user sets that.

Thanks,
Zhao



  reply	other threads:[~2024-02-29  6:54 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-20  9:24 [RFC 0/8] Introduce SMP Cache Topology Zhao Liu
2024-02-20  9:24 ` [RFC 1/8] hw/core: Rename CpuTopology to CPUTopology Zhao Liu
2024-02-20  9:24 ` [RFC 2/8] hw/core: Move CPU topology enumeration into arch-agnostic file Zhao Liu
2024-02-28  9:53   ` JeeHeng Sia
2024-02-29  4:46     ` Zhao Liu
2024-02-20  9:24 ` [RFC 3/8] hw/core: Define cache topology for machine Zhao Liu
2024-02-20  9:25 ` [RFC 4/8] hw/core: Add cache topology options in -smp Zhao Liu
2024-02-21 12:46   ` Markus Armbruster
2024-02-21 15:17     ` Zhao Liu
2024-02-26 15:39   ` Jonathan Cameron via
2024-02-27  9:20     ` Zhao Liu
2024-02-27  9:12       ` Daniel P. Berrangé
2024-02-27 10:35         ` Zhao Liu
2024-02-27 10:51       ` Jonathan Cameron via
2024-02-27 15:55         ` Zhao Liu
2024-02-28  5:38   ` JeeHeng Sia
2024-02-29  7:04     ` Zhao Liu [this message]
2024-02-20  9:25 ` [RFC 5/8] i386/cpu: Support thread and module level cache topology Zhao Liu
2024-02-20  9:25 ` [RFC 6/8] i386/cpu: Update cache topology with machine's configuration Zhao Liu
2024-02-28  9:45   ` JeeHeng Sia
2024-02-29  7:19     ` Zhao Liu
2024-02-20  9:25 ` [RFC 7/8] i386/pc: Support cache topology in -smp for PC machine Zhao Liu
2024-02-20  9:25 ` [RFC 8/8] qemu-options: Add the cache topology description of -smp Zhao Liu
2024-02-26 15:47   ` Jonathan Cameron via
2024-02-27 16:17     ` Zhao Liu
2024-02-20 20:07 ` [RFC 0/8] Introduce SMP Cache Topology Philippe Mathieu-Daudé

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