From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFB59C27C4F for ; Thu, 13 Jun 2024 05:41:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sHdCW-0005qI-Vt; Thu, 13 Jun 2024 01:40:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sHdCN-0005pr-Ep; Thu, 13 Jun 2024 01:40:35 -0400 Received: from 59-120-53-16.hinet-ip.hinet.net ([59.120.53.16] helo=mail.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sHdCK-0007yx-Ol; Thu, 13 Jun 2024 01:40:34 -0400 Received: from ethan84-VirtualBox (10.0.12.12) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 Jun 2024 13:34:12 +0800 Date: Thu, 13 Jun 2024 13:34:05 +0800 To: Jim Shu CC: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" , Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Eduardo Habkost , Marcel Apfelbaum , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Yanan Wang , Peter Xu , David Hildenbrand , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Song Gao , "Laurent Vivier" , Aurelien Jarno , "Jiaxun Yang" , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , "open list:ARM TCG CPUs" , "open list:PowerPC TCG CPUs" , "open list:S390 TCG CPUs" Subject: Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU Message-ID: References: <20240612081416.29704-1-jim.shu@sifive.com> <20240612081416.29704-3-jim.shu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240612081416.29704-3-jim.shu@sifive.com> User-Agent: Mutt/2.1.4 (2021-12-11) X-Originating-IP: [10.0.12.12] Received-SPF: pass client-ip=59.120.53.16; envelope-from=ethan84@andestech.com; helo=mail.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote: > [EXTERNAL MAIL] > > It is the preparation patch for upcoming RISC-V wgChecker device. > > Since RISC-V wgChecker could permit access in RO/WO permission, the > IOMMUMemoryRegion could return different section for read & write > access. The memory access from CPU should also pass the access_type to > IOMMU translate function so that IOMMU could return the correct section > of specified access_type. > Hi Jim, Does this method take into account the situation where the CPU access type is different from the access type when creating iotlb? I think the section might be wrong in this situation. Thanks, Ethan > >