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[35.190.215.205]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cdfab7d4sm1654148f8f.113.2024.07.09.00.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 00:21:20 -0700 (PDT) Date: Tue, 9 Jul 2024 07:21:16 +0000 From: Mostafa Saleh To: Jean-Philippe Brucker Cc: qemu-arm@nongnu.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-devel@nongnu.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org Subject: Re: [PATCH v4 18/19] hw/arm/smmuv3: Advertise S2FWB Message-ID: References: <20240701110241.2005222-1-smostafa@google.com> <20240701110241.2005222-19-smostafa@google.com> <20240704183658.GO1693268@myrica> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240704183658.GO1693268@myrica> Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=smostafa@google.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Jean, On Thu, Jul 04, 2024 at 07:36:58PM +0100, Jean-Philippe Brucker wrote: > On Mon, Jul 01, 2024 at 11:02:40AM +0000, Mostafa Saleh wrote: > > QEMU doesn's support memory attributes, so FWB is NOP, this > > might change in the future if memory attributre would be supported. > > > > Signed-off-by: Mostafa Saleh > > --- > > hw/arm/smmuv3.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > > index 807f26f2da..88378e83dd 100644 > > --- a/hw/arm/smmuv3.c > > +++ b/hw/arm/smmuv3.c > > @@ -287,6 +287,14 @@ static void smmuv3_init_regs(SMMUv3State *s) > > if (FIELD_EX32(s->idr[0], IDR0, S2P)) { > > /* XNX is a stage-2-specific feature */ > > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1); > > + if (FIELD_EX32(s->idr[0], IDR0, S1P)) { > > Why is this check needed? > I thought that only made sense only for nested SMMUs, but I guess in practice it’s not important for qemu and Linux doesn’t use it, I can just drop this patch. Thanks, Mostafa > > > + /* > > + * QEMU doesn's support memory attributes, so FWB is NOP, this > > doesn't > > Thanks, > Jean > > > + * might change in the future if memory attributre would be > > + * supported. > > + */ > > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, FWB, 1); > > + } > > } > > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); > > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); > > -- > > 2.45.2.803.g4e1b14247a-goog > >