* [PULL 0/3] loongarch-to-apply queue
@ 2024-07-19 2:26 Song Gao
2024-07-19 2:26 ` [PULL 1/3] target/loongarch/gdbstub: Add vector registers support Song Gao
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Song Gao @ 2024-07-19 2:26 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson
The following changes since commit 23fa74974d8c96bc95cbecc0d4e2d90f984939f6:
Merge tag 'pull-target-arm-20240718' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-19 07:02:17 +1000)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240719
for you to fetch changes up to 3ed016f525c8010e66be62d3ca6829eaa9b7cfb5:
hw/loongarch: Modify flash block size to 256K (2024-07-19 10:40:04 +0800)
----------------------------------------------------------------
pull-loongarch-20240719
----------------------------------------------------------------
Song Gao (2):
target/loongarch/gdbstub: Add vector registers support
hw/loongarch: Remove unimplemented extioi INT_encode mode
Xianglai Li (1):
hw/loongarch: Modify flash block size to 256K
configs/targets/loongarch64-linux-user.mak | 2 +-
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-lasx.xml | 60 ++++++++++++++++++++++++
gdb-xml/loongarch-lsx.xml | 59 ++++++++++++++++++++++++
include/hw/intc/loongarch_extioi.h | 1 -
include/hw/loongarch/virt.h | 2 +-
target/loongarch/gdbstub.c | 73 +++++++++++++++++++++++++++++-
7 files changed, 193 insertions(+), 6 deletions(-)
create mode 100644 gdb-xml/loongarch-lasx.xml
create mode 100644 gdb-xml/loongarch-lsx.xml
^ permalink raw reply [flat|nested] 8+ messages in thread* [PULL 1/3] target/loongarch/gdbstub: Add vector registers support 2024-07-19 2:26 [PULL 0/3] loongarch-to-apply queue Song Gao @ 2024-07-19 2:26 ` Song Gao 2024-07-19 2:26 ` [PULL 2/3] hw/loongarch: Remove unimplemented extioi INT_encode mode Song Gao ` (2 subsequent siblings) 3 siblings, 0 replies; 8+ messages in thread From: Song Gao @ 2024-07-19 2:26 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Philippe Mathieu-Daudé, Bibo Mao GDB already support LoongArch vector extension[1], QEMU gdb adds LoongArch vector registers support, so that users can use 'info all-registers' to get all vector registers values. [1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f383a3d5a88ee07d0c2401bd95613c222e Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewd-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240711024454.3075183-1-gaosong@loongson.cn> --- configs/targets/loongarch64-linux-user.mak | 2 +- configs/targets/loongarch64-softmmu.mak | 2 +- gdb-xml/loongarch-lasx.xml | 60 ++++++++++++++++++ gdb-xml/loongarch-lsx.xml | 59 +++++++++++++++++ target/loongarch/gdbstub.c | 73 +++++++++++++++++++++- 5 files changed, 192 insertions(+), 4 deletions(-) create mode 100644 gdb-xml/loongarch-lasx.xml create mode 100644 gdb-xml/loongarch-lsx.xml diff --git a/configs/targets/loongarch64-linux-user.mak b/configs/targets/loongarch64-linux-user.mak index d878e5a113..ea9b7e839a 100644 --- a/configs/targets/loongarch64-linux-user.mak +++ b/configs/targets/loongarch64-linux-user.mak @@ -1,4 +1,4 @@ # Default configuration for loongarch64-linux-user TARGET_ARCH=loongarch64 TARGET_BASE_ARCH=loongarch -TARGET_XML_FILES=gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml +TARGET_XML_FILES=gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index 65b65e0c34..ce19ab6a16 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -2,6 +2,6 @@ TARGET_ARCH=loongarch64 TARGET_BASE_ARCH=loongarch TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_SUPPORTS_MTTCG=y -TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml +TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml # all boards require libfdt TARGET_NEED_FDT=y diff --git a/gdb-xml/loongarch-lasx.xml b/gdb-xml/loongarch-lasx.xml new file mode 100644 index 0000000000..753b982c65 --- /dev/null +++ b/gdb-xml/loongarch-lasx.xml @@ -0,0 +1,60 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2022-2024 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.loongarch.lasx"> + <vector id="v8f32" type="ieee_single" count="8"/> + <vector id="v4f64" type="ieee_double" count="4"/> + <vector id="v32i8" type="int8" count="32"/> + <vector id="v16i16" type="int16" count="16"/> + <vector id="v8i32" type="int32" count="8"/> + <vector id="v4i64" type="int64" count="4"/> + <vector id="v2ui128" type="uint128" count="2"/> + + <union id="lasxv"> + <field name="v8_float" type="v8f32"/> + <field name="v4_double" type="v4f64"/> + <field name="v32_int8" type="v32i8"/> + <field name="v16_int16" type="v16i16"/> + <field name="v8_int32" type="v8i32"/> + <field name="v4_int64" type="v4i64"/> + <field name="v2_uint128" type="v2ui128"/> + </union> + + <reg name="xr0" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr1" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr2" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr3" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr4" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr5" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr6" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr7" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr8" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr9" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr10" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr11" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr12" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr13" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr14" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr15" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr16" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr17" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr18" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr19" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr20" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr21" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr22" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr23" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr24" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr25" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr26" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr27" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr28" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr29" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr30" bitsize="256" type="lasxv" group="lasx"/> + <reg name="xr31" bitsize="256" type="lasxv" group="lasx"/> +</feature> diff --git a/gdb-xml/loongarch-lsx.xml b/gdb-xml/loongarch-lsx.xml new file mode 100644 index 0000000000..51af1c6fd5 --- /dev/null +++ b/gdb-xml/loongarch-lsx.xml @@ -0,0 +1,59 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2022-2024 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.loongarch.lsx"> + <vector id="v4f32" type="ieee_single" count="4"/> + <vector id="v2f64" type="ieee_double" count="2"/> + <vector id="v16i8" type="int8" count="16"/> + <vector id="v8i16" type="int16" count="8"/> + <vector id="v4i32" type="int32" count="4"/> + <vector id="v2i64" type="int64" count="2"/> + + <union id="lsxv"> + <field name="v4_float" type="v4f32"/> + <field name="v2_double" type="v2f64"/> + <field name="v16_int8" type="v16i8"/> + <field name="v8_int16" type="v8i16"/> + <field name="v4_int32" type="v4i32"/> + <field name="v2_int64" type="v2i64"/> + <field name="uint128" type="uint128"/> + </union> + + <reg name="vr0" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr1" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr2" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr3" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr4" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr5" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr6" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr7" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr8" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr9" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr10" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr11" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr12" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr13" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr14" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr15" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr16" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr17" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr18" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr19" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr20" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr21" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr22" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr23" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr26" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr25" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr26" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr27" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr28" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr29" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr30" bitsize="128" type="lsxv" group="lsx"/> + <reg name="vr31" bitsize="128" type="lsxv" group="lsx"/> +</feature> diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index a0e1439bd0..7ca245ee81 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -116,8 +116,77 @@ static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) return length; } +#define VREG_NUM 32 +#define REG64_LEN 64 + +static int loongarch_gdb_get_vec(CPUState *cs, GByteArray *mem_buf, int n, int vl) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + int i, length = 0; + + if (0 <= n && n < VREG_NUM) { + for (i = 0; i < vl / REG64_LEN; i++) { + length += gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(i)); + } + } + + return length; +} + +static int loongarch_gdb_set_vec(CPUState *cs, uint8_t *mem_buf, int n, int vl) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + int i, length = 0; + + if (0 <= n && n < VREG_NUM) { + for (i = 0; i < vl / REG64_LEN; i++) { + env->fpr[n].vreg.D(i) = ldq_le_p(mem_buf + 8 * i); + length += 8; + } + } + + return length; +} + +static int loongarch_gdb_get_lsx(CPUState *cs, GByteArray *mem_buf, int n) +{ + return loongarch_gdb_get_vec(cs, mem_buf, n, LSX_LEN); +} + +static int loongarch_gdb_set_lsx(CPUState *cs, uint8_t *mem_buf, int n) +{ + return loongarch_gdb_set_vec(cs, mem_buf, n, LSX_LEN); +} + +static int loongarch_gdb_get_lasx(CPUState *cs, GByteArray *mem_buf, int n) +{ + return loongarch_gdb_get_vec(cs, mem_buf, n, LASX_LEN); +} + +static int loongarch_gdb_set_lasx(CPUState *cs, uint8_t *mem_buf, int n) +{ + return loongarch_gdb_set_vec(cs, mem_buf, n, LASX_LEN); +} + void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) { - gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu, - gdb_find_static_feature("loongarch-fpu.xml"), 0); + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + + if (FIELD_EX32(env->cpucfg[2], CPUCFG2, FP)) { + gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu, + gdb_find_static_feature("loongarch-fpu.xml"), 0); + } + + if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LSX)) { + gdb_register_coprocessor(cs, loongarch_gdb_get_lsx, loongarch_gdb_set_lsx, + gdb_find_static_feature("loongarch-lsx.xml"), 0); + } + + if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LASX)) { + gdb_register_coprocessor(cs, loongarch_gdb_get_lasx, loongarch_gdb_set_lasx, + gdb_find_static_feature("loongarch-lasx.xml"), 0); + } } -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PULL 2/3] hw/loongarch: Remove unimplemented extioi INT_encode mode 2024-07-19 2:26 [PULL 0/3] loongarch-to-apply queue Song Gao 2024-07-19 2:26 ` [PULL 1/3] target/loongarch/gdbstub: Add vector registers support Song Gao @ 2024-07-19 2:26 ` Song Gao 2024-07-19 2:26 ` [PULL 3/3] hw/loongarch: Modify flash block size to 256K Song Gao 2024-07-19 20:39 ` [PULL 0/3] loongarch-to-apply queue Richard Henderson 3 siblings, 0 replies; 8+ messages in thread From: Song Gao @ 2024-07-19 2:26 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Bibo Mao Remove extioi INT_encode encode mode, because we don't emulate it. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240718083254.748179-1-gaosong@loongson.cn> --- include/hw/intc/loongarch_extioi.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h index eccc2e0d18..626a37dfa1 100644 --- a/include/hw/intc/loongarch_extioi.h +++ b/include/hw/intc/loongarch_extioi.h @@ -50,7 +50,6 @@ #define EXTIOI_HAS_CPU_ENCODE (3) #define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \ | BIT(EXTIOI_HAS_ENABLE_OPTION) \ - | BIT(EXTIOI_HAS_INT_ENCODE) \ | BIT(EXTIOI_HAS_CPU_ENCODE)) #define EXTIOI_VIRT_CONFIG (0x4) #define EXTIOI_ENABLE (1) -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PULL 3/3] hw/loongarch: Modify flash block size to 256K 2024-07-19 2:26 [PULL 0/3] loongarch-to-apply queue Song Gao 2024-07-19 2:26 ` [PULL 1/3] target/loongarch/gdbstub: Add vector registers support Song Gao 2024-07-19 2:26 ` [PULL 2/3] hw/loongarch: Remove unimplemented extioi INT_encode mode Song Gao @ 2024-07-19 2:26 ` Song Gao 2024-07-19 8:12 ` Philippe Mathieu-Daudé 2024-07-19 20:39 ` [PULL 0/3] loongarch-to-apply queue Richard Henderson 3 siblings, 1 reply; 8+ messages in thread From: Song Gao @ 2024-07-19 2:26 UTC (permalink / raw) To: qemu-devel; +Cc: richard.henderson, Xianglai Li From: Xianglai Li <lixianglai@loongson.cn> loongarch added a common library for edk2 to parse flash base addresses through fdt. For compatibility with other architectures, the flash block size in qemu is now changed to 256k. Signed-off-by: Xianglai Li <lixianglai@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240624033319.999631-1-lixianglai@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> --- include/hw/loongarch/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..603c1cebdb 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -20,7 +20,7 @@ #define VIRT_FWCFG_BASE 0x1e020000UL #define VIRT_BIOS_BASE 0x1c000000UL #define VIRT_BIOS_SIZE (16 * MiB) -#define VIRT_FLASH_SECTOR_SIZE (128 * KiB) +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) #define VIRT_FLASH0_BASE VIRT_BIOS_BASE #define VIRT_FLASH0_SIZE VIRT_BIOS_SIZE #define VIRT_FLASH1_BASE 0x1d000000UL -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PULL 3/3] hw/loongarch: Modify flash block size to 256K 2024-07-19 2:26 ` [PULL 3/3] hw/loongarch: Modify flash block size to 256K Song Gao @ 2024-07-19 8:12 ` Philippe Mathieu-Daudé 2024-07-19 8:18 ` Daniel P. Berrangé 0 siblings, 1 reply; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-07-19 8:12 UTC (permalink / raw) To: Song Gao, qemu-devel, Daniel P. Berrangé Cc: richard.henderson, Xianglai Li, Peter Xu, Fabiano Rosas On 19/7/24 04:26, Song Gao wrote: > From: Xianglai Li <lixianglai@loongson.cn> > > loongarch added a common library for edk2 to > parse flash base addresses through fdt. > For compatibility with other architectures, > the flash block size in qemu is now changed to 256k. > > Signed-off-by: Xianglai Li <lixianglai@loongson.cn> > Reviewed-by: Song Gao <gaosong@loongson.cn> > Message-Id: <20240624033319.999631-1-lixianglai@loongson.cn> > Signed-off-by: Song Gao <gaosong@loongson.cn> > --- > include/hw/loongarch/virt.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h > index 8fdfacf268..603c1cebdb 100644 > --- a/include/hw/loongarch/virt.h > +++ b/include/hw/loongarch/virt.h > @@ -20,7 +20,7 @@ > #define VIRT_FWCFG_BASE 0x1e020000UL > #define VIRT_BIOS_BASE 0x1c000000UL > #define VIRT_BIOS_SIZE (16 * MiB) > -#define VIRT_FLASH_SECTOR_SIZE (128 * KiB) > +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) Again, I believe this breaks machine migration. See the recent example Daniel explained to me: https://lore.kernel.org/qemu-devel/Zn6EQ39Q57KtmKPU@redhat.com/ ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PULL 3/3] hw/loongarch: Modify flash block size to 256K 2024-07-19 8:12 ` Philippe Mathieu-Daudé @ 2024-07-19 8:18 ` Daniel P. Berrangé 2024-07-19 9:22 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 8+ messages in thread From: Daniel P. Berrangé @ 2024-07-19 8:18 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: Song Gao, qemu-devel, richard.henderson, Xianglai Li, Peter Xu, Fabiano Rosas On Fri, Jul 19, 2024 at 10:12:20AM +0200, Philippe Mathieu-Daudé wrote: > On 19/7/24 04:26, Song Gao wrote: > > From: Xianglai Li <lixianglai@loongson.cn> > > > > loongarch added a common library for edk2 to > > parse flash base addresses through fdt. > > For compatibility with other architectures, > > the flash block size in qemu is now changed to 256k. > > > > Signed-off-by: Xianglai Li <lixianglai@loongson.cn> > > Reviewed-by: Song Gao <gaosong@loongson.cn> > > Message-Id: <20240624033319.999631-1-lixianglai@loongson.cn> > > Signed-off-by: Song Gao <gaosong@loongson.cn> > > --- > > include/hw/loongarch/virt.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h > > index 8fdfacf268..603c1cebdb 100644 > > --- a/include/hw/loongarch/virt.h > > +++ b/include/hw/loongarch/virt.h > > @@ -20,7 +20,7 @@ > > #define VIRT_FWCFG_BASE 0x1e020000UL > > #define VIRT_BIOS_BASE 0x1c000000UL > > #define VIRT_BIOS_SIZE (16 * MiB) > > -#define VIRT_FLASH_SECTOR_SIZE (128 * KiB) > > +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) > > Again, I believe this breaks machine migration. See the recent > example Daniel explained to me: > https://lore.kernel.org/qemu-devel/Zn6EQ39Q57KtmKPU@redhat.com/ Yes, changing flash size breaks migration compat, but note that loongarch does not have any versioned machine types, so it has zero migration compat right now regardles of this change. IOW, now is the right time to make the change, before someone asks for versioned machines with loongarch. With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PULL 3/3] hw/loongarch: Modify flash block size to 256K 2024-07-19 8:18 ` Daniel P. Berrangé @ 2024-07-19 9:22 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-07-19 9:22 UTC (permalink / raw) To: Daniel P. Berrangé Cc: Song Gao, qemu-devel, richard.henderson, Xianglai Li, Peter Xu, Fabiano Rosas On 19/7/24 10:18, Daniel P. Berrangé wrote: > On Fri, Jul 19, 2024 at 10:12:20AM +0200, Philippe Mathieu-Daudé wrote: >> On 19/7/24 04:26, Song Gao wrote: >>> From: Xianglai Li <lixianglai@loongson.cn> >>> >>> loongarch added a common library for edk2 to >>> parse flash base addresses through fdt. >>> For compatibility with other architectures, >>> the flash block size in qemu is now changed to 256k. >>> >>> Signed-off-by: Xianglai Li <lixianglai@loongson.cn> >>> Reviewed-by: Song Gao <gaosong@loongson.cn> >>> Message-Id: <20240624033319.999631-1-lixianglai@loongson.cn> >>> Signed-off-by: Song Gao <gaosong@loongson.cn> >>> --- >>> include/hw/loongarch/virt.h | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h >>> index 8fdfacf268..603c1cebdb 100644 >>> --- a/include/hw/loongarch/virt.h >>> +++ b/include/hw/loongarch/virt.h >>> @@ -20,7 +20,7 @@ >>> #define VIRT_FWCFG_BASE 0x1e020000UL >>> #define VIRT_BIOS_BASE 0x1c000000UL >>> #define VIRT_BIOS_SIZE (16 * MiB) >>> -#define VIRT_FLASH_SECTOR_SIZE (128 * KiB) >>> +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) >> >> Again, I believe this breaks machine migration. See the recent >> example Daniel explained to me: >> https://lore.kernel.org/qemu-devel/Zn6EQ39Q57KtmKPU@redhat.com/ > > Yes, changing flash size breaks migration compat, but note that loongarch > does not have any versioned machine types, so it has zero migration compat > right now regardles of this change. IOW, now is the right time to make the > change, before someone asks for versioned machines with loongarch. Oh I see now, thanks for clarifying! It would have been nice to mention that in the commit description, but too late so I don't mind. Regards, Phil. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PULL 0/3] loongarch-to-apply queue 2024-07-19 2:26 [PULL 0/3] loongarch-to-apply queue Song Gao ` (2 preceding siblings ...) 2024-07-19 2:26 ` [PULL 3/3] hw/loongarch: Modify flash block size to 256K Song Gao @ 2024-07-19 20:39 ` Richard Henderson 3 siblings, 0 replies; 8+ messages in thread From: Richard Henderson @ 2024-07-19 20:39 UTC (permalink / raw) To: Song Gao, qemu-devel On 7/19/24 12:26, Song Gao wrote: > Merge tag 'pull-target-arm-20240718' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-19 07:02:17 +1000) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240719 > > for you to fetch changes up to 3ed016f525c8010e66be62d3ca6829eaa9b7cfb5: > > hw/loongarch: Modify flash block size to 256K (2024-07-19 10:40:04 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20240719 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~ ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-07-19 20:41 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-07-19 2:26 [PULL 0/3] loongarch-to-apply queue Song Gao 2024-07-19 2:26 ` [PULL 1/3] target/loongarch/gdbstub: Add vector registers support Song Gao 2024-07-19 2:26 ` [PULL 2/3] hw/loongarch: Remove unimplemented extioi INT_encode mode Song Gao 2024-07-19 2:26 ` [PULL 3/3] hw/loongarch: Modify flash block size to 256K Song Gao 2024-07-19 8:12 ` Philippe Mathieu-Daudé 2024-07-19 8:18 ` Daniel P. Berrangé 2024-07-19 9:22 ` Philippe Mathieu-Daudé 2024-07-19 20:39 ` [PULL 0/3] loongarch-to-apply queue Richard Henderson
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