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Thu, 15 Aug 2024 23:49:29 -0700 (PDT) Date: Thu, 15 Aug 2024 23:49:27 -0700 From: Deepak Gupta To: Richard Henderson Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, pbonzini@redhat.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com Subject: Re: [PATCH v4 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp Message-ID: References: <20240816010711.3055425-1-debug@rivosinc.com> <20240816010711.3055425-6-debug@rivosinc.com> <2c1039b4-a865-458a-831c-7e66b6287a98@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <2c1039b4-a865-458a-831c-7e66b6287a98@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=debug@rivosinc.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 16, 2024 at 01:41:51PM +1000, Richard Henderson wrote: >On 8/16/24 11:06, Deepak Gupta wrote: >>@@ -1245,6 +1250,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) >> static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) >> { >>+ >> } > >Watch the unrelated changes. > >>@@ -1266,6 +1272,28 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) >> CPURISCVState *env = cpu_env(cpu); >> uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); >>+ if (ctx->fcfi_lp_expected) { >>+ /* >>+ * Since we can't look ahead to confirm that the first >>+ * instruction is a legal landing pad instruction, emit >>+ * compare-and-branch sequence that will be fixed-up in >>+ * riscv_tr_tb_stop() to either statically hit or skip an >>+ * illegal instruction exception depending on whether the >>+ * flag was lowered by translation of a CJLP or JLP as >>+ * the first instruction in the block. >>+ */ >>+ TCGv_i32 immediate; >>+ TCGLabel *l; >>+ l = gen_new_label(); >>+ immediate = tcg_temp_new_i32(); >>+ tcg_gen_movi_i32(immediate, 0); >>+ tcg_ctx->cfi_lp_check = tcg_last_op(); >>+ tcg_gen_brcondi_i32(TCG_COND_EQ, immediate, 0, l); >>+ gen_helper_raise_sw_check_excep(tcg_env, >>+ tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL)); >>+ gen_set_label(l); >>+ } >>+ > >I think this is over-complicated. > >> ctx->ol = ctx->xl; >> decode_opc(env, ctx, opcode16); >> ctx->base.pc_next += ctx->cur_insn_len; > >If we delay the check until here, then > >(1) we've decoded the opcode, and processed lpad or not. >(2) we can know that lpad will have cleared ctx->fcfi_lp_expected, > so that if it is still set here, then we didn't see an lpad. > >We can go back an insert the exception like so: > > if (ctx->fcfi_lp_expected) { > /* Emit after insn_start, i.e. before the op following insn_start. */ > tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link); > > tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > tcg_env, offsetof(CPURISCVState, sw_check_code)); > gen_helper_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > > tcg_ctx->emit_before_op = NULL; > ctx->base.is_jmp = DISAS_NORETURN; > } > Hmm. Yes this reduces complication of check. Let me do that. >Emit the store to sw_check_code directly; no need for an extra helper. >Using gen_helper_raise_exception instead of generate_exception means >we don't get a spurious pc update. > >r~