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d="scan'208";a="61828536" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.36]) by orviesa004.jf.intel.com with ESMTP; 07 Aug 2024 08:24:04 -0700 Date: Wed, 7 Aug 2024 23:39:53 +0800 From: Zhao Liu To: "Xin Li (Intel)" Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, mtosatti@redhat.com, lei4.wang@intel.com, xin3.li@intel.com Subject: Re: [PATCH v1 3/3] target/i386: Raise the highest index value used for any VMCS encoding Message-ID: References: <20240807081813.735158-1-xin@zytor.com> <20240807081813.735158-4-xin@zytor.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240807081813.735158-4-xin@zytor.com> Received-SPF: pass client-ip=192.198.163.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.144, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Xin, On Wed, Aug 07, 2024 at 01:18:12AM -0700, Xin Li (Intel) wrote: > Date: Wed, 7 Aug 2024 01:18:12 -0700 > From: "Xin Li (Intel)" > Subject: [PATCH v1 3/3] target/i386: Raise the highest index value used for > any VMCS encoding > X-Mailer: git-send-email 2.45.2 > > From: Lei Wang > > Because the index value of the VMCS field encoding of FRED injected-event > data (one of the newly added VMCS fields for FRED transitions), 0x52, is > larger than any existing index value, raise the highest index value used > for any VMCS encoding to 0x52. > > Because the index value of the VMCS field encoding of Secondary VM-exit > controls, 0x44, is larger than any existing index value, raise the highest > index value used for any VMCS encoding to 0x44. > > Co-developed-by: Xin Li > Signed-off-by: Xin Li > Signed-off-by: Lei Wang > Signed-off-by: Xin Li (Intel) > --- > target/i386/cpu.h | 1 + > target/i386/kvm/kvm.c | 9 ++++++++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 118ef9cb68..62324c3dcd 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1186,6 +1186,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); > #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 > #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 > #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 > +#define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000 It's necessary to add the corresponding feat_name to FEAT_VMX_EXIT_CTLS feat word array, which could help filter the user's settings in the -cpu. > #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 > #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 > diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c > index 31f149c990..fac5990274 100644 > --- a/target/i386/kvm/kvm.c > +++ b/target/i386/kvm/kvm.c > @@ -3694,7 +3694,14 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) > kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0, > CR4_VMXE_MASK); > > - if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) { > + if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) { > + /* FRED injected-event data (0x2052). */ > + kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52); HMM, I have the questions when I check the FRED spec. Section 9.3.4 said, (for injected-event data) "This field has uses the encoding pair 2052H/2053H." So why adjust the highest index to 0x52 other than 0x53? And it seems FRED introduces another field "original-event data" (0x2404/0x2405), why not consider this field here as well? > + } else if (f[FEAT_VMX_EXIT_CTLS] & > + VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) { > + /* Secondary VM-exit controls (0x2044). */ > + kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x44); > + } else if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) { > /* TSC multiplier (0x2032). */ > kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32); > } else { Maybe we could adjust the index in a cleaner way like x86_cpu_adjust_level(), but the current case-by-case is ok for me as well. Regards, Zhao