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Wed, 07 Aug 2024 13:15:26 -0700 (PDT) Date: Wed, 7 Aug 2024 13:15:24 -0700 From: Deepak Gupta To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Jim Shu , Andy Chiu Subject: Re: [PATCH v3 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Message-ID: References: <20240807000652.1417776-1-debug@rivosinc.com> <20240807000652.1417776-7-debug@rivosinc.com> <89e5857e-fc00-46c1-b797-1fadcf463a1e@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <89e5857e-fc00-46c1-b797-1fadcf463a1e@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=debug@rivosinc.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Aug 07, 2024 at 11:23:00AM +1000, Richard Henderson wrote: >On 8/7/24 10:06, Deepak Gupta wrote: >>diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >>index 364f3ee212..c7af430f38 100644 >>--- a/target/riscv/cpu_helper.c >>+++ b/target/riscv/cpu_helper.c >>@@ -134,6 +134,19 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, >> flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); >> } >>+ if (cpu_get_fcfien(env)) { >>+ /* >>+ * For Forward CFI, only the expectation of a lpcll at >>+ * the start of the block is tracked (which can only happen >>+ * when FCFI is enabled for the current processor mode). A jump >>+ * or call at the end of the previous TB will have updated >>+ * env->elp to indicate the expectation. >>+ */ >>+ flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, >>+ env->elp != NO_LP_EXPECTED); > >A good example why it's better to store this as bool in the first place. > >> static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) >> { >>+ DisasContext *ctx = container_of(db, DisasContext, base); >>+ >>+ if (ctx->fcfi_lp_expected) { >>+ /* >>+ * Since we can't look ahead to confirm that the first >>+ * instruction is a legal landing pad instruction, emit >>+ * compare-and-branch sequence that will be fixed-up in >>+ * riscv_tr_tb_stop() to either statically hit or skip an >>+ * illegal instruction exception depending on whether the >>+ * flag was lowered by translation of a CJLP or JLP as >>+ * the first instruction in the block. >>+ */ >>+ TCGv_i32 immediate; >>+ TCGLabel *l; >>+ l = gen_new_label(); >>+ immediate = tcg_temp_new_i32(); >>+ tcg_gen_movi_i32(immediate, 0); >>+ cfi_lp_check = tcg_last_op(); >>+ tcg_gen_brcondi_i32(TCG_COND_EQ, immediate, 0, l); >>+ gen_helper_raise_sw_check_excep(tcg_env, >>+ tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), >>+ tcg_constant_tl(MISSING_LPAD), tcg_constant_tl(0)); >>+ gen_set_label(l); >>+ /* >>+ * Despite the use of gen_exception_illegal(), the rest of >>+ * the TB needs to be generated. The TCG optimizer will >>+ * clean things up depending on which path ends up being >>+ * active. >>+ */ >>+ ctx->base.is_jmp = DISAS_NEXT; >>+ } >> } > >Again, don't do this here. >There is a reason why only DISAS_NEXT is legal: plugins. >You *must* do this in riscv_tr_translate_insn, like ARM. Sorry missed this. I remember you gave same feedack in last version. > > >r~