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From: Zhao Liu <zhao1.liu@intel.com>
To: Xiaoyao Li <xiaoyao.li@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Manish <manish.mishra@nutanix.com>,
	John Levon <john.levon@nutanix.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Marcelo Tosatti <mtosatti@redhat.com>,
	qemu-devel@nongnu.org
Subject: Re: [PATCH] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f
Date: Thu, 8 Aug 2024 18:09:04 +0800	[thread overview]
Message-ID: <ZrSZQN/AQa6BiIUu@intel.com> (raw)
In-Reply-To: <20240802072426.4016194-1-xiaoyao.li@intel.com>

Hi Xiaoyao,

Patch is generally fine for me. Just a few nits:

On Fri, Aug 02, 2024 at 03:24:26AM -0400, Xiaoyao Li wrote:
> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> index dff49fce1154..b63bce2f4c82 100644
> --- a/include/hw/i386/topology.h
> +++ b/include/hw/i386/topology.h
> @@ -207,13 +207,4 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
>      return x86_apicid_from_topo_ids(topo_info, &topo_ids);
>  }
>  
> -/*
> - * Check whether there's extended topology level (module or die)?
> - */
> -static inline bool x86_has_extended_topo(unsigned long *topo_bitmap)
> -{
> -    return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) ||
> -           test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap);
> -}
> -

[snip]

> +/*
> + * Check whether there's v2 extended topology level (module or die)?
> + */
> +bool x86_has_v2_extended_topo(X86CPU *cpu)
> +{
> +    if (cpu->enable_cpuid_0x1f) {
> +        return true;
> +    }
> +
> +    return test_bit(CPU_TOPO_LEVEL_MODULE, cpu->env.avail_cpu_topo) ||
> +           test_bit(CPU_TOPO_LEVEL_DIE, cpu->env.avail_cpu_topo);
> +}
> +

I suggest to decouple 0x1f enablement and extended topo check, since as
the comment of CPUTopoLevel said:

/*
 * CPUTopoLevel is the general i386 topology hierarchical representation,
 * ordered by increasing hierarchical relationship.
 * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
 * or AMD (CPUID[0x80000026]).
 */

The topology enumeration is generic and is not bound to the vendor.

[snip]

> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index c6cc035df3d8..211a42ffbfa6 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2110,6 +2110,9 @@ struct ArchCPU {
>      /* Compatibility bits for old machine types: */
>      bool enable_cpuid_0xb;
>  
> +    /* Force to expose cpuid 0x1f */

Maybe "Force to enable cpuid 0x1f"?

> +    bool enable_cpuid_0x1f;
> +
>      /* Enable auto level-increase for all CPUID leaves */
>      bool full_cpuid_auto_level;i

Regards,
Zhao



  parent reply	other threads:[~2024-08-08  9:53 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-02  7:24 [PATCH] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f Xiaoyao Li
2024-08-08  9:29 ` Igor Mammedov
2024-08-08 14:03   ` Xiaoyao Li
2024-08-08 10:09 ` Zhao Liu [this message]
2024-08-08 13:59   ` Xiaoyao Li
2024-08-08 14:46     ` Zhao Liu
2024-08-13  2:52       ` Xiaoyao Li
2024-08-13  7:36         ` Zhao Liu

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