From: Deepak Gupta <debug@rivosinc.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v6 13/16] target/riscv: implement zicfiss instructions
Date: Wed, 21 Aug 2024 18:00:04 -0700 [thread overview]
Message-ID: <ZsaNlBC2Ye1R9MIy@debug.ba.rivosinc.com> (raw)
In-Reply-To: <85deb108-cac1-492e-89be-0997510fde0b@linaro.org>
On Thu, Aug 22, 2024 at 10:57:10AM +1000, Richard Henderson wrote:
>On 8/22/24 07:50, Deepak Gupta wrote:
>>--- a/target/riscv/insn_trans/trans_rva.c.inc
>>+++ b/target/riscv/insn_trans/trans_rva.c.inc
>>@@ -18,6 +18,8 @@
>> * this program. If not, see <http://www.gnu.org/licenses/>.
>> */
>>+#include "exec/memop.h"
>>+
>
>Why? This will have been done long ago, within the includes of
>translate.c, the parent of this file.
>
Leftover from early versions. Thought I removed it.
Will fix it.
>>+static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a)
>>+{
>>+ if (!ctx->bcfi_enabled || a->rd == 0) {
>>+ return false;
>>+ }
>>+
>>+ TCGv dest = tcg_temp_new();
>
>dest = dest_gpr(ctx, a->rd);
Ok.
>
>
>
>r~
next prev parent reply other threads:[~2024-08-22 1:01 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-21 21:49 [PATCH v6 00/16] riscv support for control flow integrity extensions Deepak Gupta
2024-08-21 21:49 ` [PATCH v6 01/16] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 02/16] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 03/16] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 04/16] target/riscv: additional code information for sw check Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-22 0:25 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 06/16] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 07/16] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 08/16] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 09/16] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-22 0:27 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 10/16] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 11/16] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-22 0:30 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 12/16] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-22 0:43 ` Richard Henderson
2024-08-22 0:58 ` Deepak Gupta
2024-08-22 5:13 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 13/16] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-22 0:57 ` Richard Henderson
2024-08-22 1:00 ` Deepak Gupta [this message]
2024-08-21 21:50 ` [PATCH v6 14/16] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 15/16] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 16/16] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
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