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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f4f4aa0sm212083266b.213.2024.08.22.23.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 23:28:44 -0700 (PDT) Date: Fri, 23 Aug 2024 07:28:43 +0100 From: Stafford Horne To: Ahmad Fatoum Cc: qemu-devel@nongnu.org, openrisc@lists.librecores.org, "Jason A . Donenfeld" Subject: Re: [PATCH RESEND] hw/openrisc/openrisc_sim: keep serial@90000000 as default Message-ID: References: <20240822163838.3722764-1-a.fatoum@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240822163838.3722764-1-a.fatoum@pengutronix.de> Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shorne@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Note the distribution list you use here: openrisc@lists.librecores.org Is old and we should use linux-openrisc@vger.kernel.org. I will get the qemu maintainer file updated. On Thu, Aug 22, 2024 at 06:38:38PM +0200, Ahmad Fatoum wrote: > We used to only have a single UART on the platform and it was located at > address 0x90000000. When the number of UARTs was increased to 4, the > first UART remained at its location, but instead of being the first one > to be registered, it became the last. > > This caused QEMU to pick 0x90000300 as the default UART, which broke > software that hardcoded the address of 0x90000000 and expected its > output to be visible when the user configured only a single console. This makes sense but what do you mean here by DEFAULT uart? I guess you mean the one connected to qemu's stdout by default? > This caused regressions[1] in the barebox test suite when updating to a > newer QEMU. As there seems to be no good reason to register the UARTs in > inverse order, let's register them by ascending address, so existing > software can remain oblivious to the additional UART ports. This sounds good to me. I will test this out and queue to qemu after the small clarification above. Also, I will wait to see if Jason has anything to say. -Stafford > [1]: https://lore.barebox.org/barebox/707e7c50-aad1-4459-8796-0cc54bab32e2@pengutronix.de/T/#m5da26e8a799033301489a938b5d5667b81cef6ad > --- > v1 -> RESEND: > - expand addressees beyond apparently defunct openrisc@lists.librecores.org > > NOTE: I am not familiar with QEMU internals, so please let me know > if registration in inverse order served a particular purpose. > --- > hw/openrisc/openrisc_sim.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c > index bffd6f721f7b..d147b00e4817 100644 > --- a/hw/openrisc/openrisc_sim.c > +++ b/hw/openrisc/openrisc_sim.c > @@ -265,7 +265,7 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base, > serial_irq = get_cpu_irq(cpus, 0, irq_pin); > } > serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, > - serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1), > + serial_hd(uart_idx), > DEVICE_NATIVE_ENDIAN); > > /* Add device tree node for serial. */ > -- > 2.39.2 >