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From: Stafford Horne <shorne@gmail.com>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: qemu-devel@nongnu.org, "Jason A . Donenfeld" <Jason@zx2c4.com>,
	linux-openrisc@vger.kernel.org
Subject: Re: [PATCH RESEND] hw/openrisc/openrisc_sim: keep serial@90000000 as default
Date: Sun, 25 Aug 2024 06:49:33 +0100	[thread overview]
Message-ID: <ZsrF7eDccRE2jPXc@antec> (raw)
In-Reply-To: <a90fe9aa-5835-4045-b719-8764cdb037cc@pengutronix.de>

On Fri, Aug 23, 2024 at 09:23:23AM +0200, Ahmad Fatoum wrote:
> Hello Stafford,
> 
> On 23.08.24 08:28, Stafford Horne wrote:
> > Note the distribution list you use here: openrisc@lists.librecores.org
> > Is old and we should use linux-openrisc@vger.kernel.org.  I will get the qemu
> > maintainer file updated.
> 
> So this list is appropriate for all openrisc-related development and not only
> for the kernel?
> 
> > On Thu, Aug 22, 2024 at 06:38:38PM +0200, Ahmad Fatoum wrote:
> >> We used to only have a single UART on the platform and it was located at
> >> address 0x90000000. When the number of UARTs was increased to 4, the
> >> first UART remained at its location, but instead of being the first one
> >> to be registered, it became the last.
> >>
> >> This caused QEMU to pick 0x90000300 as the default UART, which broke
> >> software that hardcoded the address of 0x90000000 and expected its
> >> output to be visible when the user configured only a single console.
> > 
> > This makes sense but what do you mean here by DEFAULT uart?  I guess you mean
> > the one connected to qemu's stdout by default?
> 
> Yes. I am not keen on the QEMU terminology, but the first registered UART seems
> to have a special place. Besides being connected to QEMU's stdio by default,
> it's also used to populate /chosen/stdout-path as can be seen when dumping the dtb:
> 
>   qemu-system-or1k -kernel /dev/null -machine or1k-sim,dumpdtb=qemu.dtb -nographic
> 
> 
> >> This caused regressions[1] in the barebox test suite when updating to a
> >> newer QEMU. As there seems to be no good reason to register the UARTs in
> >> inverse order, let's register them by ascending address, so existing
> >> software can remain oblivious to the additional UART ports.
> > 
> > This sounds good to me.  I will test this out and queue to qemu after the small
> > clarification above.
> > 
> > Also, I will wait to see if Jason has anything to say.
> 
> Sure.
> 
> By the way, I botched the RESEND and forgot following two lines:
> 
>   Fixes: 777784bda468 ("hw/openrisc: support 4 serial ports in or1ksim")
>   Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> 
> Let me know if I should resend (provided there's no code changes warranting a v2).
> 

This should be fine thanks.  I will fixup the commit message and repost after a
bit of testing to ensure this does not affect other environments including
Jason's test suite which uses the 4 UARTs.

-Stafford


  reply	other threads:[~2024-08-25  5:50 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-22 16:38 [PATCH RESEND] hw/openrisc/openrisc_sim: keep serial@90000000 as default Ahmad Fatoum
2024-08-23  6:28 ` Stafford Horne
2024-08-23  7:23   ` Ahmad Fatoum
2024-08-25  5:49     ` Stafford Horne [this message]
2024-08-25 11:34   ` Jason A. Donenfeld
2024-08-25 14:09     ` Peter Maydell
2024-08-27 18:53       ` Stafford Horne
2024-08-28 15:38         ` Peter Maydell
2024-08-29 15:40           ` Stafford Horne

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