From: Deepak Gupta <debug@rivosinc.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss
Date: Thu, 29 Aug 2024 22:56:41 -0700 [thread overview]
Message-ID: <ZtFfGR94f5EwIl90@debug.ba.rivosinc.com> (raw)
In-Reply-To: <abc033ff-7638-4d2d-b2d7-65b3c88311e8@linaro.org>
On Fri, Aug 30, 2024 at 03:20:04PM +1000, Richard Henderson wrote:
>On 8/30/24 09:34, Deepak Gupta wrote:
>>+bool cpu_get_bcfien(CPURISCVState *env)
>
>It occurs to me that a better name would be "cpu_get_sspen".
>The backward cfi is merely a consequence of the shadow stack.
Want me to change cpu_get_fcfien as well to cpu_get_lpen ?
>
>>+{
>>+ /* no cfi extension, return false */
>>+ if (!env_archcpu(env)->cfg.ext_zicfiss) {
>>+ return false;
>>+ }
>>+
>>+ switch (env->priv) {
>>+ case PRV_U:
>>+ if (riscv_has_ext(env, RVS)) {
>>+ return env->senvcfg & SENVCFG_SSE;
>>+ }
>>+ return env->menvcfg & MENVCFG_SSE;
>>+#ifndef CONFIG_USER_ONLY
>>+ case PRV_S:
>>+ if (env->virt_enabled) {
>>+ return env->henvcfg & HENVCFG_SSE;
>>+ }
>>+ return env->menvcfg & MENVCFG_SSE;
>>+ case PRV_M: /* M-mode shadow stack is always on if hart implements */
>>+ return true;
>
>From the manual:
>
>Activating Zicfiss in M-mode is currently not supported. Additionally, when S-mode is not
>implemented, activation in U-mode is also not supported.
Hmm. This is a good catch.
It seems I was using an earlier spec and missed this. Or atleast
I didn't bother to check assuming that spec didn't change.
Thanks for catching it and pointing it out.
I'll fix the M-mode case by return false.
For case of,
If S-mode is not implemented then activation in U-mode is also not supported. I am thinking of
making this check during extensions validation (in case user turned zicfiss=true).
Below options:
Option 1
In `riscv_cpu_validate_set_extensions`, check for S and if S is not implemented then error out
saying that zicfiss can't be turned on.
OR
Option 2
In `riscv_cpu_validate_set_extensions`, check for S and if S is not implemented then silently
clear `ext_zicfiss` in cpu config.
I think option 1 is better.
>
>So two of the cases above are wrong.
>
>
>r~
next prev parent reply other threads:[~2024-08-30 5:57 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-29 23:34 [PATCH v12 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-08-30 2:10 ` Richard Henderson
2024-08-29 23:34 ` [PATCH v12 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-30 2:13 ` Richard Henderson
2024-08-29 23:34 ` [PATCH v12 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 08/20] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 09/20] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 10/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 11/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-30 5:20 ` Richard Henderson
2024-08-30 5:56 ` Deepak Gupta [this message]
2024-08-30 16:30 ` Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 12/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 14/20] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 15/20] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 16/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 17/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 18/20] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-29 23:34 ` [PATCH v12 20/20] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
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