From: Zhao Liu <zhao1.liu@intel.com>
To: Alireza Sanaee <alireza.sanaee@huawei.com>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
zhenyu.z.wang@intel.com, dapeng1.mi@linux.intel.com,
yongwei.ma@intel.com, armbru@redhat.com, farman@linux.ibm.com,
peter.maydell@linaro.org, mst@redhat.com, anisinha@redhat.com,
shannon.zhaosl@gmail.com, imammedo@redhat.com,
mtosatti@redhat.com, berrange@redhat.com,
richard.henderson@linaro.org, linuxarm@huwei.com,
shameerali.kolothum.thodi@huawei.com,
Jonathan.Cameron@huawei.com, jiangkunkun@huawei.com,
zhao1.liu@intel.com
Subject: Re: [RFC PATCH 0/2] Specifying cache topology on ARM
Date: Mon, 2 Sep 2024 20:23:43 +0800 [thread overview]
Message-ID: <ZtWuT4W5kKEtodyo@intel.com> (raw)
In-Reply-To: <20240902112519.00005b67@huawei.com>
On Mon, Sep 02, 2024 at 11:25:19AM +0100, Alireza Sanaee wrote:
>
> Hi Zhao,
>
> Yes, please keep me CCed.
>
> One thing that I noticed, sometimes, since you were going down the
> Intel path, some variables couldn't be NULL. But when I was gonna go
> down to ARM path, I faced some scenarios where I ended up with
> some uninit vars which is still OK but could have been avoided.
Ah I didn't get your point very clearly. Could you please figure out
those places on my patches? Then I can fix them in my next version. :)
Thanks,
Zhao
> Looking forward to the next revision.
>
> Alireza
next prev parent reply other threads:[~2024-09-02 12:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-23 12:54 [RFC PATCH 0/2] Specifying cache topology on ARM Alireza Sanaee via
2024-08-23 12:54 ` [PATCH 1/2] target/arm/tcg: increase cache level for cpu=max Alireza Sanaee via
2024-08-23 12:54 ` [PATCH 2/2] hw/acpi: add cache hierarchy node to pptt table Alireza Sanaee via
2024-08-31 11:47 ` Zhao Liu
2024-08-31 11:25 ` [RFC PATCH 0/2] Specifying cache topology on ARM Zhao Liu
2024-09-02 10:25 ` Alireza Sanaee via
2024-09-02 12:23 ` Zhao Liu [this message]
2024-09-02 11:49 ` Marcin Juszkiewicz
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