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From: Zhao Liu <zhao1.liu@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: "Daniel P . Berrangé" <berrange@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Michael S.Tsirkin" <mst@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eric Blake" <eblake@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Marcelo Tosatti" <mtosatti@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
	"Alireza Sanaee" <alireza.sanaee@huawei.com>,
	qemu-devel@nongnu.org, kvm@vger.kernel.org,
	qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
	"Zhenyu Wang" <zhenyu.z.wang@intel.com>,
	"Dapeng Mi" <dapeng1.mi@linux.intel.com>,
	"Yongwei Ma" <yongwei.ma@intel.com>,
	"Zhao Liu" <zhao1.liu@intel.com>
Subject: Re: [PATCH v2 2/7] qapi/qom: Define cache enumeration and properties
Date: Mon, 7 Oct 2024 18:48:07 +0800	[thread overview]
Message-ID: <ZwO8Z6pABtp2Zfi3@intel.com> (raw)
In-Reply-To: <20240917095126.000036f1@Huawei.com>

Hi Jonathan,

Thanks for your review and feedback!

[snip]

> > Note, define cache topology based on CPU topology level with two
> > reasons:
> > 
> >  1. In practice, a cache will always be bound to the CPU container
> >     (either private in the CPU container or shared among multiple
> >     containers), and CPU container is often expressed in terms of CPU
> >     topology level.
> >  2. The x86's cache-related CPUIDs encode cache topology based on APIC
> >     ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV
> >     relies on also requires CPU containers to help indicate the private
> 
> Really trivial but CPU Containers are a different ACPI concept.
> For PPTT they are referred to as Processor Groups. Wonderfully they
> 'might match a Processor Container in the namespace' which rather implies
> they might not.  In QEMU they always will because the next bit of the
> spec matters. "In that case this entry will match the value of the _UID
> method of the associated processor container. Where there is a match it must
> be represented."
> 
> So having said all that, CPU container is probably fine as a description.

Thanks for the explanation!

> >     shared hierarchy of the cache. Therefore, for SMP systems, it is
> >     natural to use the CPU topology hierarchy directly in QEMU to define
> >     the cache topology.
> > 
> > Suggested-by: Daniel P. Berrange <berrange@redhat.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > Tested-by: Yongwei Ma <yongwei.ma@intel.com>
>
> Seems fine but my gut would be to combine this and next patch so we can
> see how it is used (assuming no one asked for it to be separate!)

No problem. I intended to make it easier to review the QAPI part, but
these two patches were simple enough that I was happy to combine them.

> Version numbers need an update I guess.

Ah, yes!

> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Thanks!

> > +##
> > +# @SmpCachePropertiesWrapper:
> > +#
> > +# List wrapper of SmpCacheProperties.
> > +#
> > +# @caches: the list of SmpCacheProperties.
> > +#
> > +# Since 9.1
> 
> Needs updating to 9.2 I guess.

Yes, I think so, too.

Thanks,
Zhao

> > +##
> > +{ 'struct': 'SmpCachePropertiesWrapper',
> > +  'data': { 'caches': ['SmpCacheProperties'] } }
> 


  parent reply	other threads:[~2024-10-07 10:33 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-08 12:59 [PATCH v2 0/7] Introduce SMP Cache Topology Zhao Liu
2024-09-08 12:59 ` [PATCH v2 1/7] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
2024-09-08 12:59 ` [PATCH v2 2/7] qapi/qom: Define cache enumeration and properties Zhao Liu
     [not found]   ` <20240917095126.000036f1@Huawei.com>
2024-10-07 10:48     ` Zhao Liu [this message]
2024-09-08 12:59 ` [PATCH v2 3/7] hw/core: Add smp cache topology for machine Zhao Liu
     [not found]   ` <20240917100048.00001bcf@Huawei.com>
2024-10-07 11:02     ` Zhao Liu
2024-09-08 12:59 ` [PATCH v2 4/7] hw/core: Check smp cache topology support " Zhao Liu
     [not found]   ` <20240917095612.00007b5a@Huawei.com>
2024-10-07 11:12     ` Zhao Liu
2024-09-08 12:59 ` [PATCH v2 5/7] i386/cpu: Support thread and module level cache topology Zhao Liu
     [not found]   ` <20240917100508.00001907@Huawei.com>
2024-10-07 11:24     ` Zhao Liu
2024-09-08 12:59 ` [PATCH v2 6/7] i386/cpu: Update cache topology with machine's configuration Zhao Liu
     [not found]   ` <20240911110028.00001d3d@huawei.com>
2024-10-07 10:21     ` Zhao Liu
     [not found]   ` <20240917100641.000050a8@Huawei.com>
2024-10-07 11:25     ` Zhao Liu
2024-09-08 12:59 ` [PATCH v2 7/7] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
     [not found]   ` <20240917101631.00003dcb@Huawei.com>
2024-10-07 11:53     ` Zhao Liu
2024-09-10 18:23 ` [PATCH v2 0/7] Introduce SMP Cache Topology Michael S. Tsirkin
2024-12-17 14:23 ` Alireza Sanaee via
2024-12-17 16:20   ` Zhao Liu

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