From: Chao Gao <chao.gao@intel.com>
To: Zhao Liu <zhao1.liu@intel.com>
Cc: <qemu-devel@nongnu.org>, <pbonzini@redhat.com>,
<jmattson@google.com>, <pawan.kumar.gupta@linux.intel.com>,
<jon@nutanix.com>, <kvm@vger.kernel.org>
Subject: Re: [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX
Date: Wed, 9 Oct 2024 16:12:38 +0800 [thread overview]
Message-ID: <ZwY69phzk3GpGvsh@intel.com> (raw)
In-Reply-To: <ZwY1AeJPlrniISB1@intel.com>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 85ef7452c0..18ba958f46 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -1148,8 +1148,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>> [FEAT_7_2_EDX] = {
>> .type = CPUID_FEATURE_WORD,
>> .feat_names = {
>> - NULL, NULL, NULL, NULL,
>> - NULL, "mcdt-no", NULL, NULL,
>> + "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
>> + "bhi-ctrl", "mcdt-no", NULL, NULL,
>
>IIUC, these bits depend on "spec-ctrl", which indicates the presence of
>IA32_SPEC_CTRL.
>
>Then I think we'd better add dependencies in feature_dependencies[].
(+ kvm mailing list)
Thanks for pointing that out. It seems that any of these bits imply the
presence of IA32_SPEC_CTRL. According to SDM vol4, chapter 2, table 2.2,
the 'Comment' column for the IA32_SPEC_CTRL MSR states:
If any one of the enumeration conditions for defined bit field positions holds.
So, it might be more appropriate to fix KVM's handling of the
IA32_SPEC_CTRL MSR (i.e., guest_has_spec_ctrl_msr()).
what do you think?
>
>-Zhao
>
>> NULL, NULL, NULL, NULL,
>> NULL, NULL, NULL, NULL,
>> NULL, NULL, NULL, NULL,
>> --
>> 2.46.1
>>
>>
next prev parent reply other threads:[~2024-10-09 8:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-19 5:10 [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX Chao Gao
2024-10-09 7:47 ` Zhao Liu
2024-10-09 8:12 ` Chao Gao [this message]
2024-10-10 13:17 ` Paolo Bonzini
2024-10-11 4:22 ` Zhao Liu
2024-10-10 13:18 ` Paolo Bonzini
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