From: Ved Shanbhogue <ved@rivosinc.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "Clément Léger" <cleger@rivosinc.com>,
qemu-riscv@nongnu.org, "Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Atish Patra" <atishp@rivosinc.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior
Date: Fri, 11 Oct 2024 13:52:32 -0500 [thread overview]
Message-ID: <Zwlz8LUEGB4Fa611@ved-XPS-8940> (raw)
In-Reply-To: <CAKmqyKPrHtsjAnc8kX__BeHvxoMvm+MmYLWSgh5TKdx0FE8o9A@mail.gmail.com>
Alistair Francis wrote:
>> When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared
>> when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared
>> when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning
>> to VU from HS.
>
>I don't see mret being mentioned in the spec. Where do you see that
>V/SSTATUS.SDT should be cleared?
>
Ssdbltrp specifies:
In S-mode, the SRET instruction sets sstatus.SDT to 0,
and if the new privilege mode is VU, it also sets
vsstatus.SDT to 0. However, in VS-mode, only vsstatus.SDT
is set to to 0.
The MRET instructions sets sstatus.SDT to 0, if the new
privilege mode is U, VS, or VU. Additionally, if it is
VU, then vsstatus.SDT is also set to 0.
Smdbltrp specifies:
The MRET and SRET instructions, when executed in M-mode,
set the MDT bit to 0. If the new privilege mode is U, VS,
or VU, then sstatus.SDT is also set to 0. Additionally,
if it is VU, then vsstatus.SDT is also set to 0.
The MNRET instruction sets the MDT bit to 0 if the new
privilege mode is not M. If it is U, VS, or VU, then
sstatus.SDT is also set to 0. Additionally, if it is VU,
then vsstatus.SDT is also set to 0.
regards
ved
next prev parent reply other threads:[~2024-10-11 18:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-25 11:57 [PATCH v2 0/8] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions Clément Léger
2024-09-25 11:57 ` [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling Clément Léger
2024-10-11 2:49 ` Alistair Francis
2024-09-25 11:58 ` [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior Clément Léger
2024-10-11 3:13 ` Alistair Francis
2024-10-11 18:52 ` Ved Shanbhogue [this message]
2024-10-17 4:36 ` Alistair Francis
2024-10-17 18:27 ` Ved Shanbhogue
2024-10-18 2:21 ` Alistair Francis
2024-10-18 7:02 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 3/8] target/riscv: Implement Ssdbltrp exception handling Clément Léger
2024-10-11 3:22 ` Alistair Francis
2024-10-14 7:43 ` Clément Léger
2024-10-17 4:29 ` Alistair Francis
2024-10-17 7:45 ` Clément Léger
2024-10-18 2:25 ` Alistair Francis
2024-10-18 7:04 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch Clément Léger
2024-10-11 3:24 ` Alistair Francis
2024-10-14 7:43 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling Clément Léger
2024-10-11 3:30 ` Alistair Francis
2024-10-11 7:40 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret behavior Clément Léger
2024-09-25 11:58 ` [PATCH v2 7/8] target/riscv: Implement Smdbltrp behavior Clément Léger
2024-09-25 11:58 ` [PATCH v2 8/8] target/riscv: Add Smdbltrp ISA extension enable switch Clément Léger
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