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From: Tao Su <tao1.su@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, mtosatti@redhat.com, xiaoyao.li@intel.com,
	xuelian.guo@intel.com
Subject: Re: [PATCH 4/6] target/i386: Add feature dependencies for AVX10
Date: Mon, 28 Oct 2024 20:23:33 +0800	[thread overview]
Message-ID: <Zx+CRVe8fYzCnCqt@linux.bj.intel.com> (raw)
In-Reply-To: <340b5b33-8b77-43ab-b0dc-c6e9f610b4a2@redhat.com>

On Mon, Oct 28, 2024 at 11:45:25AM +0100, Paolo Bonzini wrote:
> On 10/28/24 11:02, Tao Su wrote:
> > On Mon, Oct 28, 2024 at 09:45:39AM +0100, Paolo Bonzini wrote:
> > > On 10/28/24 03:45, Tao Su wrote:
> > > > Since the highest supported vector length for a processor implies that
> > > > all lesser vector lengths are also supported, add the dependencies of
> > > > the supported vector lengths. If all vector lengths aren't supported,
> > > > clear AVX10 enable bit as well.
> > > > 
> > > > Note that the order of AVX10 related dependencies should be kept as:
> > > >           CPUID_24_0_EBX_AVX10_128     -> CPUID_24_0_EBX_AVX10_256,
> > > >           CPUID_24_0_EBX_AVX10_256     -> CPUID_24_0_EBX_AVX10_512,
> > > >           CPUID_24_0_EBX_AVX10_VL_MASK -> CPUID_7_1_EDX_AVX10,
> > > 
> > > I think you need to add a set of dependencies so that avx10 cannot be set,
> > > unless all the older AVX features that it's composed of are available.  From
> > > the manual these are
> > > 
> > > AVX512F, AVX512CD, AVX512VW, AVX512DQ, AVX512_VBMI, AVX512_IFMA,
> > > AVX512_VNNI, AVX512_BF16, AVX512_VPOPCNTDQ, AVX512_VBMI2, VAES, GFNI,
> > > VPCLMULQDQ, AVX512_BITALG, AVX512_FP16.
> > 
> > Thanks for such a quick review!!
> > 
> > AVX10.1 spec said:
> > Intel AVX-512 will continue to be supported on P-core-only processors for
> > the foreseeable future to support legacy applications. However, new vector
> > ISA features will only be added to the Intel AVX10 ISA moving forward.
> > While Intel AVX10/512 includes all Intel AVX-512 instructions, it
> > important to note that applications compiled to Intel AVX-512 with vector
> > length limited to 256 bits are not guaranteed to be compatible on an Intel
> > AVX10/256 processor.
> > 
> > I.e. AVX10/256 processors will support old AVX-512 instructions
> > (limited to 256 bits and enumerated by AVX10) but not set AVX-512 related
> > CPUIDs. So, I think we can't add these dependencies…
> 
> Of course you're right about AVX10 in general, you still need to add the
> dependency but only for CPUID_24_0_EBX_AVX10_512.
> 

I agree, will add in v2, thanks!



  reply	other threads:[~2024-10-28 12:29 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-28  2:45 [PATCH 0/6] Add AVX10.1 CPUID support and GraniteRapids-v2 model Tao Su
2024-10-28  2:45 ` [PATCH 1/6] target/i386: Add AVX512 state when AVX10 is supported Tao Su
2024-10-28  8:41   ` Paolo Bonzini
2024-10-28  9:25     ` Tao Su
2024-10-29  8:49       ` Paolo Bonzini
2024-10-29  9:29         ` Tao Su
2024-10-28 15:12   ` Xiaoyao Li
2024-10-28  2:45 ` [PATCH 2/6] target/i386: add avx10-version property Tao Su
2024-10-28 15:10   ` Xiaoyao Li
2024-10-29  6:14     ` Tao Su
2024-10-28  2:45 ` [PATCH 3/6] target/i386: Add CPUID.24 leaf for AVX10 Tao Su
2024-10-28 15:04   ` Xiaoyao Li
2024-10-29  6:13     ` Tao Su
2024-10-29  8:25   ` Paolo Bonzini
2024-10-29 14:29     ` Tao Su
2024-10-28  2:45 ` [PATCH 4/6] target/i386: Add feature dependencies " Tao Su
2024-10-28  8:45   ` Paolo Bonzini
2024-10-28 10:02     ` Tao Su
2024-10-28 10:45       ` Paolo Bonzini
2024-10-28 12:23         ` Tao Su [this message]
2024-10-28 14:48         ` Xiaoyao Li
2024-10-28 14:50           ` Paolo Bonzini
2024-10-28 15:08             ` Xiaoyao Li
2024-10-29 14:47   ` Zhao Liu
2024-10-29 14:36     ` Tao Su
2024-10-28  2:45 ` [PATCH 5/6] target/i386: Add support for AVX10 in CPUID enumeration Tao Su
2024-10-28  2:45 ` [PATCH 6/6] target/i386: Introduce GraniteRapids-v2 model Tao Su
2024-10-29 14:58   ` Zhao Liu
2024-10-30  1:28     ` Tao Su

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