From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Zhao Liu <zhao1.liu@intel.com>
Cc: "Igor Mammedov" <imammedo@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
"Alireza Sanaee" <alireza.sanaee@huawei.com>,
qemu-devel@nongnu.org, kvm@vger.kernel.org,
qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
"Zhenyu Wang" <zhenyu.z.wang@intel.com>,
"Dapeng Mi" <dapeng1.mi@linux.intel.com>,
"Yongwei Ma" <yongwei.ma@intel.com>
Subject: Re: [PATCH v3 1/7] hw/core: Make CPU topology enumeration arch-agnostic
Date: Thu, 17 Oct 2024 16:30:03 +0100 [thread overview]
Message-ID: <ZxEte1KBwWuCdkb1@redhat.com> (raw)
In-Reply-To: <20241012104429.1048908-2-zhao1.liu@intel.com>
On Sat, Oct 12, 2024 at 06:44:23PM +0800, Zhao Liu wrote:
> Cache topology needs to be defined based on CPU topology levels. Thus,
> define CPU topology enumeration in qapi/machine.json to make it generic
> for all architectures.
>
> To match the general topology naming style, rename CPU_TOPO_LEVEL_* to
> CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and
> socket.
>
> Also, enumerate additional topology levels for non-i386 arches, and add
> a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work
> with compatibility requirement of arch-specific cache topology models.
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> Tested-by: Yongwei Ma <yongwei.ma@intel.com>
> ---
> Changes since Patch v2:
> * Updated version of new QAPI structures to v9.2. (Jonathan)
>
> Changes since Patch v1:
> * Dropped prefix of CpuTopologyLevel enumeration. (Markus)
> * Rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_* to match the QAPI's
> generated code. (Markus)
>
> Changes since RFC v2:
> * Dropped cpu-topology.h and cpu-topology.c since QAPI has the helper
> (CpuTopologyLevel_str) to convert enum to string. (Markus)
> * Fixed text format in machine.json (CpuTopologyLevel naming, 2 spaces
> between sentences). (Markus)
> * Added a new level "default" to de-compatibilize some arch-specific
> topo settings. (Daniel)
> * Moved CpuTopologyLevel to qapi/machine-common.json, at where the
> cache enumeration and smp-cache object would be added.
> - If smp-cache object is defined in qapi/machine.json, storage-daemon
> will complain about the qmp cmds in qapi/machine.json during
> compiling.
>
> Changes since RFC v1:
> * Used QAPI to enumerate CPU topology levels.
> * Dropped string_to_cpu_topo() since QAPI will help to parse the topo
> levels.
> ---
> hw/i386/x86-common.c | 4 +-
> include/hw/i386/topology.h | 22 +-----
> qapi/machine-common.json | 46 +++++++++++-
> target/i386/cpu.c | 144 ++++++++++++++++++-------------------
> target/i386/cpu.h | 4 +-
> 5 files changed, 124 insertions(+), 96 deletions(-)
>
> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> index dff49fce1154..bf740383038b 100644
> --- a/include/hw/i386/topology.h
> +++ b/include/hw/i386/topology.h
> @@ -39,7 +39,7 @@
> unsigned threads_per_core;
> } X86CPUTopoInfo;
>
> -/*
> - * CPUTopoLevel is the general i386 topology hierarchical representation,
> - * ordered by increasing hierarchical relationship.
> - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
> - * or AMD (CPUID[0x80000026]).
> - */
> -enum CPUTopoLevel {
> - CPU_TOPO_LEVEL_INVALID,
> - CPU_TOPO_LEVEL_SMT,
> - CPU_TOPO_LEVEL_CORE,
> - CPU_TOPO_LEVEL_MODULE,
> - CPU_TOPO_LEVEL_DIE,
> - CPU_TOPO_LEVEL_PACKAGE,
> - CPU_TOPO_LEVEL_MAX,
> -};
> -
snip
> @@ -18,3 +18,47 @@
> ##
> { 'enum': 'S390CpuEntitlement',
> 'data': [ 'auto', 'low', 'medium', 'high' ] }
> +
> +##
> +# @CpuTopologyLevel:
> +#
> +# An enumeration of CPU topology levels.
> +#
> +# @invalid: Invalid topology level.
Previously all topology levels were internal to QEMU, and IIUC
this CPU_TOPO_LEVEL_INVALID appears to have been a special
value to indicate the cache was absent ?
Now we're exposing this directly to the user as a settable
option. We need to explain what effect setting 'invalid'
has on the CPU cache config.
> +#
> +# @thread: thread level, which would also be called SMT level or
> +# logical processor level. The @threads option in
> +# SMPConfiguration is used to configure the topology of this
> +# level.
> +#
> +# @core: core level. The @cores option in SMPConfiguration is used
> +# to configure the topology of this level.
> +#
> +# @module: module level. The @modules option in SMPConfiguration is
> +# used to configure the topology of this level.
> +#
> +# @cluster: cluster level. The @clusters option in SMPConfiguration
> +# is used to configure the topology of this level.
> +#
> +# @die: die level. The @dies option in SMPConfiguration is used to
> +# configure the topology of this level.
> +#
> +# @socket: socket level, which would also be called package level.
> +# The @sockets option in SMPConfiguration is used to configure
> +# the topology of this level.
> +#
> +# @book: book level. The @books option in SMPConfiguration is used
> +# to configure the topology of this level.
> +#
> +# @drawer: drawer level. The @drawers option in SMPConfiguration is
> +# used to configure the topology of this level.
> +#
> +# @default: default level. Some architectures will have default
> +# topology settings (e.g., cache topology), and this special
> +# level means following the architecture-specific settings.
With regards,
Daniel
--
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next prev parent reply other threads:[~2024-10-17 15:30 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-12 10:44 [PATCH v3 0/7] Introduce SMP Cache Topology Zhao Liu
2024-10-12 10:44 ` [PATCH v3 1/7] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
[not found] ` <20241017095227.00006d85@Huawei.com>
2024-10-17 13:20 ` Jonathan Cameron via
2024-10-17 14:51 ` Zhao Liu
2024-10-17 15:30 ` Daniel P. Berrangé [this message]
2024-10-18 2:36 ` Zhao Liu
2024-10-18 7:55 ` Daniel P. Berrangé
2024-10-18 9:01 ` Zhao Liu
2024-10-17 16:19 ` Marcin Juszkiewicz
2024-10-18 4:26 ` Zhao Liu
2024-10-12 10:44 ` [PATCH v3 2/7] qapi/qom: Define cache enumeration and properties for machine Zhao Liu
2024-10-12 10:44 ` [PATCH v3 3/7] hw/core: Check smp cache topology support " Zhao Liu
2024-10-12 10:44 ` [PATCH v3 4/7] i386/cpu: Support thread and module level cache topology Zhao Liu
2024-10-12 10:44 ` [PATCH v3 5/7] i386/cpu: Update cache topology with machine's configuration Zhao Liu
2024-10-12 10:44 ` [PATCH v3 6/7] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
2024-10-17 15:27 ` Daniel P. Berrangé
2024-10-18 3:57 ` Zhao Liu
2024-10-18 7:58 ` Daniel P. Berrangé
2024-10-18 9:03 ` Zhao Liu
2024-10-12 10:44 ` [PATCH v3 7/7] i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu
2024-10-17 13:16 ` Jonathan Cameron via
2024-10-17 13:19 ` [PATCH v3 0/7] Introduce SMP Cache Topology Jonathan Cameron via
[not found] ` <20241017141402.0000135b@Huawei.com>
2024-10-17 15:01 ` Zhao Liu
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