From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Zhao Liu <zhao1.liu@intel.com>
Cc: "Igor Mammedov" <imammedo@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
"Alireza Sanaee" <alireza.sanaee@huawei.com>,
qemu-devel@nongnu.org, kvm@vger.kernel.org,
qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
"Zhenyu Wang" <zhenyu.z.wang@intel.com>,
"Dapeng Mi" <dapeng1.mi@linux.intel.com>
Subject: Re: [PATCH v3 1/7] hw/core: Make CPU topology enumeration arch-agnostic
Date: Fri, 18 Oct 2024 08:55:35 +0100 [thread overview]
Message-ID: <ZxIUd9tMi9o1UVOS@redhat.com> (raw)
In-Reply-To: <ZxHJri+rgdGKf/0L@intel.com>
On Fri, Oct 18, 2024 at 10:36:30AM +0800, Zhao Liu wrote:
> Hi Daniel,
>
> > > -/*
> > > - * CPUTopoLevel is the general i386 topology hierarchical representation,
> > > - * ordered by increasing hierarchical relationship.
> > > - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
> > > - * or AMD (CPUID[0x80000026]).
> > > - */
> > > -enum CPUTopoLevel {
> > > - CPU_TOPO_LEVEL_INVALID,
> > > - CPU_TOPO_LEVEL_SMT,
> > > - CPU_TOPO_LEVEL_CORE,
> > > - CPU_TOPO_LEVEL_MODULE,
> > > - CPU_TOPO_LEVEL_DIE,
> > > - CPU_TOPO_LEVEL_PACKAGE,
> > > - CPU_TOPO_LEVEL_MAX,
> > > -};
> > > -
> >
> > snip
> >
> > > @@ -18,3 +18,47 @@
> > > ##
> > > { 'enum': 'S390CpuEntitlement',
> > > 'data': [ 'auto', 'low', 'medium', 'high' ] }
> > > +
> > > +##
> > > +# @CpuTopologyLevel:
> > > +#
> > > +# An enumeration of CPU topology levels.
> > > +#
> > > +# @invalid: Invalid topology level.
> >
> > Previously all topology levels were internal to QEMU, and IIUC
> > this CPU_TOPO_LEVEL_INVALID appears to have been a special
> > value to indicate the cache was absent ?
>
> Now I haven't support this logic.
> x86 CPU has a "l3-cache" property, and maybe that property can be
> implemented or replaced by the "invalid" level support you mentioned.
>
> > Now we're exposing this directly to the user as a settable
> > option. We need to explain what effect setting 'invalid'
> > has on the CPU cache config.
>
> If user set "invalid", QEMU will report the error message:
>
> qemu-system-x86_64: Invalid cache topology level: invalid. The topology should match valid CPU topology level
>
> Do you think this error message is sufficient?
If the user cannot set 'invalid' as an input, and no QEMU interface
will emit, then ideally we would not define 'invalid' in the QAPI
schema at all.
This woudl require us to have some internal only way to record
"invalid", separately from the topology level, or with a magic
internal only constant that doesn't clash with the public enum
constants. I guess the latter would be less work e.g. we could
"abuse" the 'MAX' constant value
#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL_MAX
or separate it with a negative value
#define CPU_TOPOLOGY_LEVEL_INVALID -1
With regards,
Daniel
--
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next prev parent reply other threads:[~2024-10-18 7:56 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-12 10:44 [PATCH v3 0/7] Introduce SMP Cache Topology Zhao Liu
2024-10-12 10:44 ` [PATCH v3 1/7] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
[not found] ` <20241017095227.00006d85@Huawei.com>
2024-10-17 13:20 ` Jonathan Cameron via
2024-10-17 14:51 ` Zhao Liu
2024-10-17 15:30 ` Daniel P. Berrangé
2024-10-18 2:36 ` Zhao Liu
2024-10-18 7:55 ` Daniel P. Berrangé [this message]
2024-10-18 9:01 ` Zhao Liu
2024-10-17 16:19 ` Marcin Juszkiewicz
2024-10-18 4:26 ` Zhao Liu
2024-10-12 10:44 ` [PATCH v3 2/7] qapi/qom: Define cache enumeration and properties for machine Zhao Liu
2024-10-12 10:44 ` [PATCH v3 3/7] hw/core: Check smp cache topology support " Zhao Liu
2024-10-12 10:44 ` [PATCH v3 4/7] i386/cpu: Support thread and module level cache topology Zhao Liu
2024-10-12 10:44 ` [PATCH v3 5/7] i386/cpu: Update cache topology with machine's configuration Zhao Liu
2024-10-12 10:44 ` [PATCH v3 6/7] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
2024-10-17 15:27 ` Daniel P. Berrangé
2024-10-18 3:57 ` Zhao Liu
2024-10-18 7:58 ` Daniel P. Berrangé
2024-10-18 9:03 ` Zhao Liu
2024-10-12 10:44 ` [PATCH v3 7/7] i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu
2024-10-17 13:16 ` Jonathan Cameron via
2024-10-17 13:19 ` [PATCH v3 0/7] Introduce SMP Cache Topology Jonathan Cameron via
[not found] ` <20241017141402.0000135b@Huawei.com>
2024-10-17 15:01 ` Zhao Liu
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