From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FD94D0C609 for ; Fri, 25 Oct 2024 12:55:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4Jqr-0006zK-I4; Fri, 25 Oct 2024 08:55:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4Jqp-0006sB-In for qemu-devel@nongnu.org; Fri, 25 Oct 2024 08:55:35 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4Jqn-0004xO-4C for qemu-devel@nongnu.org; Fri, 25 Oct 2024 08:55:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1729860932; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:in-reply-to:in-reply-to: references:references; bh=e77XIlvulyf/f9Y8TZIkfwjukkAPIINCx9VWzDIMND4=; b=Yh4zE0jRcJ1wYouTnoDcokh7P5cX0e6/wcm22jb0yV2T67jUS6w1o/7IHbKhl48baIAJeq KgNuqU408NadKFvFBJkzqpf59bVMIvYSQtVdABJFbLlxYZ1627Y7cf2LVhS45iw3rlSt2r gUzTmak9+xpG/3cu9ChxLNx9O+5de/w= Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-134-wj34u_MyPpag_U4is72eEw-1; Fri, 25 Oct 2024 08:55:30 -0400 X-MC-Unique: wj34u_MyPpag_U4is72eEw-1 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 225771956048; Fri, 25 Oct 2024 12:55:28 +0000 (UTC) Received: from redhat.com (unknown [10.42.28.164]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 994B519560A2; Fri, 25 Oct 2024 12:55:22 +0000 (UTC) Date: Fri, 25 Oct 2024 13:55:19 +0100 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Eric Auger Cc: eric.auger.pro@gmail.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, abologna@redhat.com, jdenemar@redhat.com, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: Re: [RFC 13/21] arm/cpu: Add infra to handle generated ID register definitions Message-ID: References: <20241025101959.601048-1-eric.auger@redhat.com> <20241025101959.601048-14-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20241025101959.601048-14-eric.auger@redhat.com> User-Agent: Mutt/2.2.12 (2023-09-09) X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass client-ip=170.10.133.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.454, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Oct 25, 2024 at 12:17:32PM +0200, Eric Auger wrote: > The known ID regs are described in a new initialization function > dubbed initialize_cpu_sysreg_properties(). That code will be > automatically generated from linux arch/arm64/tools/sysreg. For the > time being let's just describe a single id reg, CTR_EL0. In this > description we only care about non RES/RAZ fields, ie. named fields. > > The registers are populated in a 3x8x8 array and their fields are > added in a sorted list. > > Signed-off-by: Eric Auger > --- > target/arm/cpu-custom.h | 58 ++++++++++++++++++++++++++++++ > target/arm/cpu-sysreg-properties.c | 41 +++++++++++++++++++++ > target/arm/cpu64.c | 2 ++ > target/arm/meson.build | 1 + > 4 files changed, 102 insertions(+) > create mode 100644 target/arm/cpu-custom.h > create mode 100644 target/arm/cpu-sysreg-properties.c > > diff --git a/target/arm/cpu-custom.h b/target/arm/cpu-custom.h > new file mode 100644 > index 0000000000..1952095bf7 > --- /dev/null > +++ b/target/arm/cpu-custom.h > @@ -0,0 +1,58 @@ > +#ifndef ARM_CPU_CUSTOM_H > +#define ARM_CPU_CUSTOM_H License header her. > diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-properties.c > new file mode 100644 > index 0000000000..753e7c9127 > --- /dev/null > +++ b/target/arm/cpu-sysreg-properties.c > @@ -0,0 +1,41 @@ > +/* > + * QEMU ARM CPU SYSREG PROPERTIES > + * to be generated from linux sysreg > + * > + * Copyright (c) 2024, Inc. 2024 ^^^^ missing company name :-) > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see > + * > + */ > + > +#include "cpu-custom.h" > + > +ARM64SysReg arm64_id_regs[NR_ID_REGS]; > + > +void initialize_cpu_sysreg_properties(void) > +{ > + memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NR_ID_REGS); ^^^ just sizeof(arm64_id_regs) > + /* CTR_EL0 */ > + ARM64SysReg *CTR_EL0 = arm64_sysreg_get(3, 3, 0, 0, 1); > + CTR_EL0->name = "CTR_EL0"; > + arm64_sysreg_add_field(CTR_EL0, "TMinline", 32, 37); > + arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29); > + arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28); > + arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27); > + arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23); > + arm64_sysreg_add_field(CTR_EL0, "DMinLine", 16, 19); > + arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15); > + arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3); > +} > + With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|