From: Zhao Liu <zhao1.liu@intel.com>
To: Dongli Zhang <dongli.zhang@oracle.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, pbonzini@redhat.com,
mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com,
likexu@tencent.com, like.xu.linux@gmail.com,
zhenyuw@linux.intel.com, groug@kaod.org, lyan@digitalocean.com,
khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com,
den@virtuozzo.com, joe.jin@oracle.com,
davydov-max@yandex-team.ru
Subject: Re: [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE unavailable
Date: Wed, 6 Nov 2024 11:54:04 +0800 [thread overview]
Message-ID: <ZyroXEOsRPonKD7x@intel.com> (raw)
In-Reply-To: <20241104094119.4131-2-dongli.zhang@oracle.com>
Hi Dongli,
On Mon, Nov 04, 2024 at 01:40:16AM -0800, Dongli Zhang wrote:
> Date: Mon, 4 Nov 2024 01:40:16 -0800
> From: Dongli Zhang <dongli.zhang@oracle.com>
> Subject: [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE
> unavailable
> X-Mailer: git-send-email 2.43.5
>
> When the PERFCORE is disabled with "-cpu host,-perfctr-core", it is
> reflected in in guest dmesg.
>
> [ 0.285136] Performance Events: AMD PMU driver.
>
> However, the guest cpuid indicates the PerfMonV2 is still available.
>
> CPU:
> Extended Performance Monitoring and Debugging (0x80000022):
> AMD performance monitoring V2 = true
> AMD LBR V2 = false
> AMD LBR stack & PMC freezing = false
> number of core perf ctrs = 0x6 (6)
> number of LBR stack entries = 0x0 (0)
> number of avail Northbridge perf ctrs = 0x0 (0)
> number of available UMC PMCs = 0x0 (0)
> active UMCs bitmask = 0x0
>
> Disable PerfMonV2 in cpuid when PERFCORE is disabled.
>
> Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
> Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
> ---
> target/i386/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 3baa95481f..4490a7a8d6 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -7103,6 +7103,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> *eax = *ebx = *ecx = *edx = 0;
> /* AMD Extended Performance Monitoring and Debug */
> if (kvm_enabled() && cpu->enable_pmu &&
> + (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_PERFCORE) &&
> (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) {
> *eax |= CPUID_8000_0022_EAX_PERFMON_V2;
> *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count,
You can define dependency like this:
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3baa95481fbc..99c69ec9f369 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1803,6 +1803,10 @@ static FeatureDep feature_dependencies[] = {
.from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
.to = { FEAT_24_0_EBX, ~0ull },
},
+ {
+ .from = { FEAT_8000_0001_ECX, CPUID_EXT3_PERFCORE },
+ .to = { FEAT_8000_0022_EAX, CPUID_8000_0022_EAX_PERFMON_V2 }
+ }
};
typedef struct X86RegisterInfo32 {
---
Does this meet your needs?
Regards,
Zhao
next prev parent reply other threads:[~2024-11-06 3:37 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-04 9:40 [PATCH 0/7] target/i386/kvm/pmu: Enhancement, Bugfix and Cleanup Dongli Zhang
2024-11-04 9:40 ` [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE unavailable Dongli Zhang
2024-11-06 3:54 ` Zhao Liu [this message]
2024-11-07 0:29 ` dongli.zhang
2024-11-07 7:57 ` Zhao Liu
2024-11-04 9:40 ` [PATCH 2/7] target/i386/kvm: introduce 'pmu-cap-disabled' to set KVM_PMU_CAP_DISABLE Dongli Zhang
2024-11-07 7:52 ` Zhao Liu
2024-11-07 23:44 ` dongli.zhang
2024-11-08 2:32 ` Zhao Liu
2024-11-08 12:52 ` Sandipan Das
2024-11-13 17:15 ` Zhao Liu
2024-11-14 0:13 ` dongli.zhang
2024-11-21 10:06 ` Mi, Dapeng
2025-02-07 9:52 ` Mi, Dapeng
2025-02-09 20:12 ` dongli.zhang
2025-02-10 8:04 ` Mi, Dapeng
2024-11-04 9:40 ` [PATCH 3/7] target/i386/kvm: init PMU information only once Dongli Zhang
2024-11-10 15:29 ` Zhao Liu
2024-11-13 1:50 ` dongli.zhang
2024-11-13 16:48 ` Zhao Liu
2024-11-04 9:40 ` [PATCH 4/7] target/i386/kvm: rename architectural PMU variables Dongli Zhang
2024-11-04 9:40 ` [PATCH 5/7] target/i386/kvm: reset AMD PMU registers during VM reset Dongli Zhang
2024-11-06 9:58 ` Sandipan Das
2024-11-07 0:33 ` dongli.zhang
2024-11-07 21:00 ` Maksim Davydov
2024-11-08 1:19 ` dongli.zhang
2024-11-08 14:07 ` Maksim Davydov
2024-11-08 18:04 ` dongli.zhang
2024-11-04 9:40 ` [PATCH 6/7] target/i386/kvm: support perfmon-v2 for reset Dongli Zhang
2024-11-08 13:09 ` Sandipan Das
2024-11-08 16:55 ` dongli.zhang
2024-11-04 9:40 ` [PATCH 7/7] target/i386/kvm: don't stop Intel PMU counters Dongli Zhang
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