From: Zhao Liu <zhao1.liu@intel.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
qemu-devel@nongnu.org,
"Daniel P . Berrange" <berrange@redhat.com>,
"Yongwei Ma" <yongwei.ma@intel.com>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>
Subject: Re: [PULL 09/29] qapi/qom: Define cache enumeration and properties for machine
Date: Sun, 10 Nov 2024 22:04:52 +0800 [thread overview]
Message-ID: <ZzC9hCPd7vbGrGDa@intel.com> (raw)
In-Reply-To: <CAFEAcA_+ZSZF1VYFcPRq1AD+i4=nT2RsdVhhaj7wiL4xD=R_-A@mail.gmail.com>
Hi Peter,
On Fri, Nov 08, 2024 at 07:10:42PM +0000, Peter Maydell wrote:
> Date: Fri, 8 Nov 2024 19:10:42 +0000
> From: Peter Maydell <peter.maydell@linaro.org>
> Subject: Re: [PULL 09/29] qapi/qom: Define cache enumeration and properties
> for machine
>
> On Tue, 5 Nov 2024 at 22:49, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
> >
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > The x86 and ARM need to allow user to configure cache properties
> > (current only topology):
> > * For x86, the default cache topology model (of max/host CPU) does not
> > always match the Host's real physical cache topology. Performance can
> > increase when the configured virtual topology is closer to the
> > physical topology than a default topology would be.
> > * For ARM, QEMU can't get the cache topology information from the CPU
> > registers, then user configuration is necessary. Additionally, the
> > cache information is also needed for MPAM emulation (for TCG) to
> > build the right PPTT.
> >
>
> Hi; Coverity points out an issue with this change (CID 1565389):
>
> > diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
> > index 5d8d7edcbd3..c6d90cd6d41 100644
> > --- a/hw/core/machine-smp.c
> > +++ b/hw/core/machine-smp.c
> > @@ -261,6 +261,31 @@ void machine_parse_smp_config(MachineState *ms,
> > }
> > }
> >
> > +bool machine_parse_smp_cache(MachineState *ms,
> > + const SmpCachePropertiesList *caches,
> > + Error **errp)
> > +{
> > + const SmpCachePropertiesList *node;
> > + DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX);
>
> DECLARE_BITMAP() defines the caches_bitmap bitmap, but it
> does not initialize it...
Yes, I missed this...
> > +
> > + for (node = caches; node; node = node->next) {
> > + /* Prohibit users from repeating settings. */
> > + if (test_bit(node->value->cache, caches_bitmap)) {
>
> ...so here we are reading the variable when it is uninitialized.
>
> If you want to zero-initialize the bitmap you can use
> bitmap_zero(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX);
Thank you for your advice! I'll submit a patch to fix this!
Regards,
Zhao
next prev parent reply other threads:[~2024-11-10 13:47 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-05 22:46 [PULL 00/29] Misc HW patches for 2024-11-05 Philippe Mathieu-Daudé
2024-11-05 22:46 ` [PULL 01/29] target/microblaze: Rename CPU endianness property as 'little-endian' Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 02/29] hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 03/29] hw/microblaze/s3adsp1800: Explicit CPU endianness Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 04/29] hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpio Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 05/29] hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macro Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 06/29] hw/core/machine: Add missing 'units.h' and 'error-report.h' headers Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 07/29] i386/cpu: Don't enumerate the "invalid" CPU topology level Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 08/29] hw/core: Make CPU topology enumeration arch-agnostic Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 09/29] qapi/qom: Define cache enumeration and properties for machine Philippe Mathieu-Daudé
2024-11-08 19:10 ` Peter Maydell
2024-11-10 14:04 ` Zhao Liu [this message]
2024-11-05 22:47 ` [PULL 10/29] hw/core: Check smp cache topology support " Philippe Mathieu-Daudé
2024-11-08 19:16 ` Peter Maydell
2024-11-10 14:12 ` Zhao Liu
2024-11-05 22:47 ` [PULL 11/29] hw/core: Add a helper to check the cache topology level Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 12/29] hw/ppc/e500: Prefer QOM cast Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 13/29] hw/ppc/e500: Remove unused "irqs" parameter Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 14/29] hw/ppc/e500: Add missing device tree properties to i2c controller node Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 15/29] hw/ppc/mpc8544_guts: Populate POR PLL ratio status register Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 16/29] hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 17/29] hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 18/29] hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 19/29] hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 20/29] hw/net/fsl_etsec/miim: Reuse MII constants Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 21/29] hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 22/29] hw/gpio/mpc8xxx: " Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 23/29] hw/ppc/mpc8544_guts: " Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 24/29] hw/sd/sdhci: " Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 25/29] hw/block/pflash_cfi01: " Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 26/29] hw/i2c/smbus_eeprom: " Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 27/29] hw/rtc/ds1338: " Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 28/29] hw/usb/hcd-ehci-sysbus: " Philippe Mathieu-Daudé
2024-11-05 22:47 ` [PULL 29/29] hw/riscv/iommu: fix build error with clang Philippe Mathieu-Daudé
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