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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381fbf416c6sm9099754f8f.54.2024.11.12.23.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 23:00:37 -0800 (PST) Date: Wed, 13 Nov 2024 07:00:35 +0000 From: Stafford Horne To: Joel Holdsworth Cc: qemu-devel@nongnu.org Subject: Re: [PATCH] hw/openrisc: Fixed undercounting of TTCR in continuous mode Message-ID: References: <20240607222933.45791-1-jholdsworth@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240607222933.45791-1-jholdsworth@nvidia.com> Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=shorne@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Jun 07, 2024 at 03:29:33PM -0700, Joel Holdsworth via wrote: > In the existing design, TTCR is prone to undercounting when running in > continuous mode. This manifests as a timer interrupt appearing to > trigger a few cycles prior to the deadline set in SPR_TTMR_TP. > > When the timer triggers, the virtual time delta in nanoseconds between > the time when the timer was set, and when it triggers is calculated. > This nanoseconds value is then divided by TIMER_PERIOD (50) to compute > an increment of cycles to apply to TTCR. > > However, this calculation rounds down the number of cycles causing the > undercounting. > > A simplistic solution would be to instead round up the number of cycles, > however this will result in the accumulation of timing error over time. > > This patch corrects the issue by calculating the time delta in > nanoseconds between when the timer was last reset and the timer event. > This approach allows the TTCR value to be rounded up, but without > accumulating error over time. > > Signed-off-by: Joel Holdsworth > --- > hw/openrisc/cputimer.c | 22 +++++++++++++--------- > 1 file changed, 13 insertions(+), 9 deletions(-) > > diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c > index 835986c4db..ddc129aa48 100644 > --- a/hw/openrisc/cputimer.c > +++ b/hw/openrisc/cputimer.c > @@ -29,7 +29,8 @@ > /* Tick Timer global state to allow all cores to be in sync */ > typedef struct OR1KTimerState { > uint32_t ttcr; > - uint64_t last_clk; > + uint32_t ttcr_offset; > + uint64_t clk_offset; > } OR1KTimerState; > > static OR1KTimerState *or1k_timer; > @@ -37,6 +38,8 @@ static OR1KTimerState *or1k_timer; > void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) > { > or1k_timer->ttcr = val; > + or1k_timer->ttcr_offset = val; > + or1k_timer->clk_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > } > > uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) > @@ -53,9 +56,8 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu) > return; > } > now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > - or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk) > - / TIMER_PERIOD); > - or1k_timer->last_clk = now; > + or1k_timer->ttcr = (now - or1k_timer->clk_offset + TIMER_PERIOD - 1) / TIMER_PERIOD + > + or1k_timer->ttcr_offset; > } > > /* Update the next timeout time as difference between ttmr and ttcr */ > @@ -69,7 +71,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) > } > > cpu_openrisc_count_update(cpu); > - now = or1k_timer->last_clk; > + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > > if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) { > wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; > @@ -110,7 +112,8 @@ static void openrisc_timer_cb(void *opaque) > case TIMER_NONE: > break; > case TIMER_INTR: > - or1k_timer->ttcr = 0; > + /* Zero the count by applying a negative offset to the counter */ > + or1k_timer->ttcr_offset += UINT32_MAX - (cpu->env.ttmr & TTMR_TP); Hi Joel, I am trying to get this merged as I am finally getting some time for this again after a long project at work. Why here do you do += UINT32_MAX - (cpu->env.ttmr & TTMR_TP)? Is there an edge case I am not thinking of that is making you use UINT32_MAX? Wouldn't this be the same as r1k_timer->ttcr_offset -= 1 - (cpu->env.ttmr & TTMR_TP); -Stafford