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[213.67.3.247]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53d826af003sm2225079e87.265.2024.11.13.07.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2024 07:34:33 -0800 (PST) Date: Wed, 13 Nov 2024 16:34:33 +0100 From: "Edgar E. Iglesias" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Richard Henderson , Peter Maydell , Anton Johansson , Jason Wang , qemu-arm@nongnu.org, =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , Thomas Huth , Alistair Francis , Paolo Bonzini , Gustavo Romero Subject: Re: [PATCH 18/20] hw/net/xilinx_ethlite: Map TX_CTRL as MMIO Message-ID: References: <20241112181044.92193-1-philmd@linaro.org> <20241112181044.92193-19-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241112181044.92193-19-philmd@linaro.org> User-Agent: Mutt/2.2.12 (2023-09-09) Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Nov 12, 2024 at 07:10:42PM +0100, Philippe Mathieu-Daudé wrote: > Add TX_CTRL to the TX registers MMIO region. > Reviewed-by: Edgar E. Iglesias > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/net/xilinx_ethlite.c | 56 +++++++++++++++++++---------------------- > 1 file changed, 26 insertions(+), 30 deletions(-) > > diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c > index f7a5b1620a..f681b91769 100644 > --- a/hw/net/xilinx_ethlite.c > +++ b/hw/net/xilinx_ethlite.c > @@ -39,10 +39,8 @@ > > #define R_TX_BUF0 0 > #define A_TX_BASE0 0x07f4 > -#define R_TX_CTRL0 (0x07fc / 4) > #define R_TX_BUF1 (0x0800 / 4) > #define A_TX_BASE1 0x0ff4 > -#define R_TX_CTRL1 (0x0ffc / 4) > > #define R_RX_BUF0 (0x1000 / 4) > #define A_RX_BASE0 0x17fc > @@ -55,6 +53,7 @@ > enum { > TX_LEN = 0, > TX_GIE = 1, > + TX_CTRL = 2, > TX_MAX > }; > > @@ -71,6 +70,7 @@ enum { > > typedef struct XlnxXpsEthLitePort > { > + MemoryRegion txio; > MemoryRegion rxio; > > struct { > @@ -143,6 +143,9 @@ static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) > case TX_GIE: > r = s->port[port_index].reg.tx_gie; > break; > + case TX_CTRL: > + r = s->port[port_index].reg.tx_ctrl; > + break; > default: > g_assert_not_reached(); > } > @@ -154,6 +157,7 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, > unsigned int size) > { > XlnxXpsEthLite *s = opaque; > + unsigned port_index = addr_to_port_index(addr); > > switch (addr >> 2) { > case TX_LEN: > @@ -162,6 +166,26 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, > case TX_GIE: > s->port[port_index].reg.tx_gie = value; > break; > + case TX_CTRL: > + if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { > + qemu_send_packet(qemu_get_queue(s->nic), > + txbuf_ptr(s, port_index), > + s->port[port_index].reg.tx_len); > + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { > + eth_pulse_irq(s); > + } > + } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { > + memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); > + if (s->port[port_index].reg.tx_ctrl & CTRL_I) { > + eth_pulse_irq(s); > + } > + } > + /* > + * We are fast and get ready pretty much immediately > + * so we actually never flip the S nor P bits to one. > + */ > + s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); > + break; > default: > g_assert_not_reached(); > } > @@ -232,18 +256,12 @@ static uint64_t > eth_read(void *opaque, hwaddr addr, unsigned int size) > { > XlnxXpsEthLite *s = opaque; > - unsigned port_index = addr_to_port_index(addr); > uint32_t r = 0; > > addr >>= 2; > > switch (addr) > { > - case R_TX_CTRL1: > - case R_TX_CTRL0: > - r = s->port[port_index].reg.tx_ctrl; > - break; > - > default: > r = tswap32(s->regs[addr]); > break; > @@ -256,33 +274,11 @@ eth_write(void *opaque, hwaddr addr, > uint64_t val64, unsigned int size) > { > XlnxXpsEthLite *s = opaque; > - unsigned int port_index = addr_to_port_index(addr); > uint32_t value = val64; > > addr >>= 2; > switch (addr) > { > - case R_TX_CTRL0: > - case R_TX_CTRL1: > - if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { > - qemu_send_packet(qemu_get_queue(s->nic), > - txbuf_ptr(s, port_index), > - s->port[port_index].reg.tx_len); > - if (s->port[port_index].reg.tx_ctrl & CTRL_I) { > - eth_pulse_irq(s); > - } > - } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { > - memcpy(&s->conf.macaddr.a[0], txbuf_ptr(s, port_index), 6); > - if (s->port[port_index].reg.tx_ctrl & CTRL_I) { > - eth_pulse_irq(s); > - } > - } > - > - /* We are fast and get ready pretty much immediately so > - we actually never flip the S nor P bits to one. */ > - s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); > - break; > - > default: > s->regs[addr] = tswap32(value); > break; > -- > 2.45.2 >