qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Mostafa Saleh <smostafa@google.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	eric.auger@redhat.com, peter.maydell@linaro.org, jgg@nvidia.com,
	nicolinc@nvidia.com, ddutile@redhat.com, linuxarm@huawei.com,
	wangzhou1@hisilicon.com, jiangkunkun@huawei.com,
	jonathan.cameron@huawei.com, zhangfei.gao@linaro.org
Subject: Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3
Date: Wed, 13 Nov 2024 16:16:36 +0000	[thread overview]
Message-ID: <ZzTQ5Dn8ckIJjxc-@google.com> (raw)
In-Reply-To: <20241108125242.60136-1-shameerali.kolothum.thodi@huawei.com>

Hi Shameer,

On Fri, Nov 08, 2024 at 12:52:37PM +0000, Shameer Kolothum via wrote:
> Hi,
> 
> This series adds initial support for a user-creatable "arm-smmuv3-nested"
> device to Qemu. At present the Qemu ARM SMMUv3 emulation is per machine
> and cannot support multiple SMMUv3s.
> 

I had a quick look at the SMMUv3 files, as now SMMUv3 supports nested
translation emulation, would it make sense to rename this? As AFAIU,
this is about virt (stage-1) SMMUv3 that is emulated to a guest.
Including vSMMU or virt would help distinguish the code, as now
some new function as smmu_nested_realize() looks confusing.

Thanks,
Mostafa

> In order to support vfio-pci dev assignment with vSMMUv3, the physical
> SMMUv3 has to be configured in nested mode. Having a pluggable
> "arm-smmuv3-nested" device enables us to have multiple vSMMUv3 for Guests
> running on a host with multiple physical SMMUv3s. A few benefits of doing
> this are,
> 
> 1. Avoid invalidation broadcast or lookup in case devices are behind
>    multiple phys SMMUv3s.
> 2. Makes it easy to handle phys SMMUv3s that differ in features.
> 3. Easy to handle future requirements such as vCMDQ support.
> 
> This is based on discussions/suggestions received for a previous RFC by
> Nicolin here[0].
> 
> This series includes,
>  -Adds support for "arm-smmuv3-nested" device. At present only virt is
>   supported and is using _plug_cb() callback to hook the sysbus mem
>   and irq (Not sure this has any negative repercussions). Patch #3.
>  -Provides a way to associate a pci-bus(pxb-pcie) to the above device.
>   Patch #3.
>  -The last patch is adding RMR support for MSI doorbell handling. Patch #5.
>   This may change in future[1].
> 
> This RFC is for initial discussion/test purposes only and includes patches
> that are only relevant for adding the "arm-smmuv3-nested" support. For the
> complete branch please find,
> https://github.com/hisilicon/qemu/tree/private-smmuv3-nested-dev-rfc-v1
> 
> Few ToDos to note,
> 1. At present default-bus-bypass-iommu=on should be set when
>    arm-smmuv3-nested dev is specified. Otherwise you may get an IORT
>    related boot error.  Requires fixing.
> 2. Hot adding a device is not working at the moment. Looks like pcihp irq issue.
>    Could be a bug in IORT id mappings.
> 3. The above branch doesn't support vSVA yet.
> 
> Hopefully this is helpful in taking the discussion forward. Please take a
> look and let me know.
> 
> How to use it(Eg:):
> 
> On a HiSilicon platform that has multiple physical SMMUv3s, the ACC ZIP VF
> devices and HNS VF devices are behind different SMMUv3s. So for a Guest,
> specify two smmuv3-nested devices each behind a pxb-pcie as below,
> 
> ./qemu-system-aarch64 -machine virt,gic-version=3,default-bus-bypass-iommu=on \
> -enable-kvm -cpu host -m 4G -smp cpus=8,maxcpus=8 \
> -object iommufd,id=iommufd0 \
> -bios QEMU_EFI.fd \
> -kernel Image \
> -device virtio-blk-device,drive=fs \
> -drive if=none,file=rootfs.qcow2,id=fs \
> -device pxb-pcie,id=pcie.1,bus_nr=8,bus=pcie.0 \
> -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1 \
> -device arm-smmuv3-nested,id=smmuv1,pci-bus=pcie.1 \
> -device vfio-pci,host=0000:7d:02.1,bus=pcie.port1,iommufd=iommufd0 \
> -device pxb-pcie,id=pcie.2,bus_nr=16,bus=pcie.0 \
> -device pcie-root-port,id=pcie.port2,bus=pcie.2,chassis=2 \
> -device arm-smmuv3-nested,id=smmuv2,pci-bus=pcie.2 \
> -device vfio-pci,host=0000:75:00.1,bus=pcie.port2,iommufd=iommufd0 \
> -append "rdinit=init console=ttyAMA0 root=/dev/vda2 rw earlycon=pl011,0x9000000" \
> -device virtio-9p-pci,fsdev=p9fs2,mount_tag=p9,bus=pcie.0 \
> -fsdev local,id=p9fs2,path=p9root,security_model=mapped \
> -net none \
> -nographic
> 
> Guest will boot with two SMMuv3s,
> [    1.608130] arm-smmu-v3 arm-smmu-v3.0.auto: option mask 0x0
> [    1.609655] arm-smmu-v3 arm-smmu-v3.0.auto: ias 48-bit, oas 48-bit (features 0x00020b25)
> [    1.612475] arm-smmu-v3 arm-smmu-v3.0.auto: allocated 65536 entries for cmdq
> [    1.614444] arm-smmu-v3 arm-smmu-v3.0.auto: allocated 32768 entries for evtq
> [    1.617451] arm-smmu-v3 arm-smmu-v3.1.auto: option mask 0x0
> [    1.618842] arm-smmu-v3 arm-smmu-v3.1.auto: ias 48-bit, oas 48-bit (features 0x00020b25)
> [    1.621366] arm-smmu-v3 arm-smmu-v3.1.auto: allocated 65536 entries for cmdq
> [    1.623225] arm-smmu-v3 arm-smmu-v3.1.auto: allocated 32768 entries for evtq
> 
> With a pci topology like below,
> [root@localhost ~]# lspci -tv
> -+-[0000:00]-+-00.0  Red Hat, Inc. QEMU PCIe Host bridge
>  |           +-01.0  Red Hat, Inc. QEMU PCIe Expander bridge
>  |           +-02.0  Red Hat, Inc. QEMU PCIe Expander bridge
>  |           \-03.0  Virtio: Virtio filesystem
>  +-[0000:08]---00.0-[09]----00.0  Huawei Technologies Co., Ltd. HNS Network Controller (Virtual Function)
>  \-[0000:10]---00.0-[11]----00.0  Huawei Technologies Co., Ltd. HiSilicon ZIP Engine(Virtual Function)
> [root@localhost ~]#
> 
> And if you want to add another HNS VF, it should be added to the same SMMUv3
> as of the first HNS dev,
> 
> -device pcie-root-port,id=pcie.port3,bus=pcie.1,chassis=3 \
> -device vfio-pci,host=0000:7d:02.2,bus=pcie.port3,iommufd=iommufd0 \
> 
> [root@localhost ~]# lspci -tv
> -+-[0000:00]-+-00.0  Red Hat, Inc. QEMU PCIe Host bridge
>  |           +-01.0  Red Hat, Inc. QEMU PCIe Expander bridge
>  |           +-02.0  Red Hat, Inc. QEMU PCIe Expander bridge
>  |           \-03.0  Virtio: Virtio filesystem
>  +-[0000:08]-+-00.0-[09]----00.0  Huawei Technologies Co., Ltd. HNS Network Controller (Virtual Function)
>  |           \-01.0-[0a]----00.0  Huawei Technologies Co., Ltd. HNS Network Controller (Virtual Function)
>  \-[0000:10]---00.0-[11]----00.0  Huawei Technologies Co., Ltd. HiSilicon ZIP Engine(Virtual Function)
> [root@localhost ~]#
> 
> Attempt to add the HNS VF to a different SMMUv3 will result in,
> 
> -device vfio-pci,host=0000:7d:02.2,bus=pcie.port3,iommufd=iommufd0: Unable to attach viommu
> -device vfio-pci,host=0000:7d:02.2,bus=pcie.port3,iommufd=iommufd0: vfio 0000:7d:02.2:
>    Failed to set iommu_device: [iommufd=29] error attach 0000:7d:02.2 (38) to id=11: Invalid argument
> 
> At present Qemu is not doing any extra validation other than the above
> failure to make sure the user configuration is correct or not. The
> assumption is libvirt will take care of this.
> 
> Thanks,
> Shameer
> [0] https://lore.kernel.org/qemu-devel/cover.1719361174.git.nicolinc@nvidia.com/
> [1] https://lore.kernel.org/linux-iommu/ZrVN05VylFq8lK4q@Asurada-Nvidia/
> 
> Eric Auger (1):
>   hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested
>     binding
> 
> Nicolin Chen (2):
>   hw/arm/virt: Add an SMMU_IO_LEN macro
>   hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes
> 
> Shameer Kolothum (2):
>   hw/arm/smmuv3: Add initial support for SMMUv3 Nested device
>   hw/arm/smmuv3: Associate a pci bus with a SMMUv3 Nested device
> 
>  hw/arm/smmuv3.c          |  61 ++++++++++++++++++++++
>  hw/arm/virt-acpi-build.c | 109 ++++++++++++++++++++++++++++++++-------
>  hw/arm/virt.c            |  33 ++++++++++--
>  hw/core/sysbus-fdt.c     |   1 +
>  include/hw/arm/smmuv3.h  |  17 ++++++
>  include/hw/arm/virt.h    |  15 ++++++
>  6 files changed, 215 insertions(+), 21 deletions(-)
> 
> -- 
> 2.34.1
> 
> 


  parent reply	other threads:[~2024-11-13 16:17 UTC|newest]

Thread overview: 150+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-08 12:52 [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3 Shameer Kolothum via
2024-11-08 12:52 ` [RFC PATCH 1/5] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2024-11-13 16:48   ` Eric Auger
2024-11-08 12:52 ` [RFC PATCH 2/5] hw/arm/smmuv3: Add initial support for SMMUv3 Nested device Shameer Kolothum via
2024-11-13 17:12   ` Eric Auger
2024-11-13 18:05     ` Nicolin Chen
2024-11-26 18:28       ` Donald Dutile
2024-11-27 10:21         ` Shameerali Kolothum Thodi via
2024-11-27 16:00           ` Jason Gunthorpe
2024-11-27 16:05             ` Eric Auger
2024-11-28  3:25               ` Zhangfei Gao
2024-11-28  8:06                 ` Eric Auger
2024-11-28  8:28                   ` Shameerali Kolothum Thodi via
2024-11-28  8:41                     ` Eric Auger
2024-11-28 12:52                     ` Jason Gunthorpe
2024-11-27 23:03             ` Donald Dutile
2024-11-28 12:51               ` Jason Gunthorpe
2024-11-28  4:29           ` Donald Dutile
2024-11-28  4:44             ` Nicolin Chen
2024-11-28 12:54               ` Jason Gunthorpe
2024-11-28 18:22                 ` Nicolin Chen
2024-12-02 18:53                 ` Donald Dutile
2024-11-28  8:17             ` Shameerali Kolothum Thodi via
2024-11-14  8:20     ` Shameerali Kolothum Thodi via
2024-11-14  8:41       ` Eric Auger
2024-11-14 13:27         ` Shameerali Kolothum Thodi via
2024-11-15 22:32       ` Nicolin Chen
2024-11-13 18:00   ` Eric Auger
2024-11-08 12:52 ` [RFC PATCH 3/5] hw/arm/smmuv3: Associate a pci bus with a " Shameer Kolothum via
2024-11-13 17:58   ` Eric Auger
2024-11-14  8:30     ` Shameerali Kolothum Thodi via
2025-01-30 16:29   ` Daniel P. Berrangé
2025-01-30 18:19     ` Shameerali Kolothum Thodi via
2024-11-08 12:52 ` [RFC PATCH 4/5] hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes Shameer Kolothum via
2024-11-18 10:01   ` Eric Auger
2024-11-18 11:44     ` Shameerali Kolothum Thodi via
2024-11-18 13:45       ` Eric Auger
2024-11-18 15:00         ` Shameerali Kolothum Thodi via
2024-11-18 18:09           ` Eric Auger
2024-11-20 14:16             ` Shameerali Kolothum Thodi via
2024-11-20 16:10               ` Eric Auger
2024-11-20 16:26                 ` Shameerali Kolothum Thodi via
2024-11-21  9:46                   ` Shameerali Kolothum Thodi via
2024-12-10 20:48                     ` Nicolin Chen
2024-12-11 15:21                       ` Shameerali Kolothum Thodi via
2024-12-13  0:28                         ` Nicolin Chen
2024-11-08 12:52 ` [RFC PATCH 5/5] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding Shameer Kolothum via
2024-11-13 18:31   ` Nicolin Chen
2024-11-14  8:48     ` Shameerali Kolothum Thodi via
2024-11-14 10:41       ` Eric Auger
2024-11-15 22:12         ` Nicolin Chen
2024-12-10 23:01   ` Nicolin Chen
2024-12-11  0:48     ` Jason Gunthorpe
2024-12-11  1:28       ` Nicolin Chen
2024-12-11 13:11         ` Jason Gunthorpe
2024-12-11 17:20           ` Nicolin Chen
2024-12-11 18:01             ` Jason Gunthorpe
2024-11-12 22:59 ` [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3 Nicolin Chen
2024-11-14  7:56   ` Shameerali Kolothum Thodi via
2024-11-20 23:59   ` Nathan Chen
2024-11-21 10:12     ` Shameerali Kolothum Thodi via
2024-11-22  1:41       ` Nathan Chen
2024-11-22 17:38         ` Shameerali Kolothum Thodi via
2024-11-22 18:53           ` Nathan Chen
2025-02-04 14:00             ` Eric Auger
2024-12-13 11:58           ` Daniel P. Berrangé
2024-12-13 12:43             ` Jason Gunthorpe
2024-12-12 23:54     ` Nathan Chen
2024-12-13  1:01       ` Nathan Chen
2024-12-16  9:31         ` Shameerali Kolothum Thodi via
2025-01-25  2:43           ` Nathan Chen
2025-01-27 15:26             ` Shameerali Kolothum Thodi via
2025-01-27 23:35               ` Nathan Chen
2024-11-13 16:16 ` Mostafa Saleh [this message]
2024-11-14  8:01   ` Shameerali Kolothum Thodi via
2024-11-14 11:49     ` Mostafa Saleh
2024-11-13 21:42 ` Nicolin Chen
2024-11-14  9:11   ` Shameerali Kolothum Thodi via
2024-11-18 10:50 ` Eric Auger
2025-01-30 16:41   ` Daniel P. Berrangé
2024-12-13 12:00 ` Daniel P. Berrangé
2024-12-13 12:46   ` Jason Gunthorpe
2024-12-13 13:19     ` Daniel P. Berrangé
2024-12-16  9:38       ` Shameerali Kolothum Thodi via
2024-12-17 18:36       ` Donald Dutile
2024-12-13 13:33     ` Peter Maydell
2024-12-16 10:01       ` Shameerali Kolothum Thodi via
2025-01-09  4:45         ` Nicolin Chen
2025-01-11  4:05           ` Donald Dutile
2025-01-23  4:10             ` Nicolin Chen
2025-01-23  8:28               ` Shameerali Kolothum Thodi via
2025-01-23  8:40                 ` Nicolin Chen
2025-01-23 11:07                 ` Duan, Zhenzhong
2025-02-17  9:17                   ` Duan, Zhenzhong
2025-02-18  6:52                     ` Shameerali Kolothum Thodi via
2025-03-06 17:59                       ` Eric Auger
2025-03-06 18:27                         ` Shameerali Kolothum Thodi via
2025-03-06 18:40                           ` Eric Auger
2025-01-31 16:54           ` Eric Auger
2025-02-03 18:50             ` Nicolin Chen
2025-02-04 17:49               ` Eric Auger
2025-02-05  0:08                 ` Nicolin Chen
2025-02-05 10:43                   ` Shameerali Kolothum Thodi via
2025-02-05 12:35                   ` Eric Auger
2025-02-06 10:34                   ` Shameerali Kolothum Thodi via
2025-02-06 18:58                     ` Nicolin Chen
2025-03-03 15:21                       ` Shameerali Kolothum Thodi via
2025-03-03 17:04                         ` Nicolin Chen
2025-03-04  9:30                           ` Shameerali Kolothum Thodi via
2025-01-30 16:00 ` Daniel P. Berrangé
2025-01-30 18:09   ` Shameerali Kolothum Thodi via
2025-01-31  9:33     ` Shameerali Kolothum Thodi via
2025-01-31 10:07       ` Eric Auger
2025-01-31 14:24       ` Jason Gunthorpe
2025-01-31 14:39         ` Shameerali Kolothum Thodi via
2025-01-31 14:54           ` Jason Gunthorpe
2025-01-31 15:23             ` Shameerali Kolothum Thodi via
2025-01-31 16:08               ` Eric Auger
2025-02-05 20:53                 ` Nathan Chen
2025-02-06  8:54                   ` Daniel P. Berrangé
2025-02-06  8:53                 ` Daniel P. Berrangé
2025-02-06 16:44                   ` Eric Auger
2025-01-31 21:41     ` Daniel P. Berrangé
2025-02-06 10:02       ` Shameerali Kolothum Thodi via
2025-02-06 10:37         ` Daniel P. Berrangé
2025-02-06 13:51           ` Shameerali Kolothum Thodi via
2025-02-06 14:46             ` Daniel P. Berrangé
2025-02-06 15:07               ` Shameerali Kolothum Thodi via
2025-02-06 17:02                 ` Jason Gunthorpe
2025-02-06 17:10                   ` Daniel P. Berrangé
2025-02-06 17:46                     ` Jason Gunthorpe
2025-02-06 17:54                       ` Daniel P. Berrangé
2025-02-06 17:58                         ` Jason Gunthorpe
2025-02-06 18:04                           ` Shameerali Kolothum Thodi via
2025-02-06 18:13                             ` Jason Gunthorpe
2025-02-06 18:18                               ` Shameerali Kolothum Thodi via
2025-02-06 18:22                                 ` Jason Gunthorpe
2025-02-06 20:33                                   ` Nicolin Chen
2025-02-06 20:38                                     ` Jason Gunthorpe
2025-02-06 20:48                                       ` Nicolin Chen
2025-02-06 21:11                                         ` Jason Gunthorpe
2025-02-06 22:46                                           ` Nicolin Chen
2025-02-07  0:08                                             ` Jason Gunthorpe
2025-02-07 10:21                                     ` Shameerali Kolothum Thodi via
2025-02-07 10:31                                       ` Daniel P. Berrangé
2025-02-07 12:21                                         ` Shameerali Kolothum Thodi via
2025-02-07 12:53                                           ` Jason Gunthorpe
2025-02-06 18:18                           ` Daniel P. Berrangé
2025-02-06 17:57                       ` Shameerali Kolothum Thodi via
2025-02-06 17:59                         ` Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZzTQ5Dn8ckIJjxc-@google.com \
    --to=smostafa@google.com \
    --cc=ddutile@redhat.com \
    --cc=eric.auger@redhat.com \
    --cc=jgg@nvidia.com \
    --cc=jiangkunkun@huawei.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=linuxarm@huawei.com \
    --cc=nicolinc@nvidia.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=shameerali.kolothum.thodi@huawei.com \
    --cc=wangzhou1@hisilicon.com \
    --cc=zhangfei.gao@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).