From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52498) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuAw4-00084N-37 for qemu-devel@nongnu.org; Mon, 09 Jun 2014 21:33:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuAvy-0007kc-2a for qemu-devel@nongnu.org; Mon, 09 Jun 2014 21:33:12 -0400 Received: from mail-pb0-x22c.google.com ([2607:f8b0:400e:c01::22c]:62919) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuAvx-0007kY-Rt for qemu-devel@nongnu.org; Mon, 09 Jun 2014 21:33:06 -0400 Received: by mail-pb0-f44.google.com with SMTP id rq2so5632514pbb.31 for ; Mon, 09 Jun 2014 18:33:04 -0700 (PDT) Sender: Alistair Francis From: Alistair Francis Date: Tue, 10 Jun 2014 11:32:57 +1000 Message-Id: Subject: [Qemu-devel] [RFC v1 1/2] arm: Add the cortex-a9 CPU to the a9mpcore device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, alistair.francis@xilinx.com This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It first does a check to make sure no other CPUs exist and if they do the Cortex-A9 won't be added. This is implemented to maintain compatibility and can be removed once all machines have been updated This patch also allows the midr and reset-property to be set Signed-off-by: Alistair Francis --- There comments in the code explaining the reason that the CPU is initiated in the realize function. This is because it relies on the num_cpu property, which isn't yet set in the initfn Is this an acceptable compromise? hw/cpu/a9mpcore.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/hw/cpu/a9mpcore.h | 4 ++++ 2 files changed, 47 insertions(+), 0 deletions(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c09358c..1159044 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -21,6 +21,12 @@ static void a9mp_priv_initfn(Object *obj) { A9MPPrivState *s = A9MPCORE_PRIV(obj); + /* Ideally would init the CPUs here, but the num_cpu property has not been + * set yet. So that only works if assuming a single CPU + * object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a9-" TYPE_ARM_CPU); + * object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); + */ + memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); @@ -50,6 +56,40 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) Error *err = NULL; int i; + /* Just a temporary measure to not break machines that init the CPU + * seperatly */ + if (!first_cpu) { + s->cpu = g_malloc(sizeof(ARMCPU) * s->num_cpu); + for (i = 0; i < s->num_cpu; i++) { + object_initialize((s->cpu + i), sizeof(*(s->cpu + i)), + "cortex-a9-" TYPE_ARM_CPU); + + if (s->midr) { + object_property_set_int(OBJECT((s->cpu + i)), s->midr, + "midr", &err); + if (err) { + error_propagate(errp, err); + exit(1); + } + } + if (s->reset_cbar) { + object_property_set_int(OBJECT((s->cpu + i)), s->reset_cbar, + "reset-cbar", &err); + if (err) { + error_propagate(errp, err); + exit(1); + } + } + object_property_set_bool(OBJECT((s->cpu + i)), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + } + g_free(s->cpu); + } + scudev = DEVICE(&s->scu); qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); @@ -152,6 +192,9 @@ static Property a9mp_priv_properties[] = { * Other boards may differ and should set this property appropriately. */ DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + /* Properties for the A9 CPU */ + DEFINE_PROP_UINT32("midr", A9MPPrivState, midr, 0), + DEFINE_PROP_UINT64("reset-cbar", A9MPPrivState, reset_cbar, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h index 5d67ca2..8e395a4 100644 --- a/include/hw/cpu/a9mpcore.h +++ b/include/hw/cpu/a9mpcore.h @@ -29,6 +29,10 @@ typedef struct A9MPPrivState { MemoryRegion container; uint32_t num_irq; + ARMCPU *cpu; + uint32_t midr; + uint64_t reset_cbar; + A9SCUState scu; GICState gic; A9GTimerState gtimer; -- 1.7.1