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Fri, 07 Feb 2020 07:49:47 -0800 (PST) Received: from [10.43.13.93] ([135.196.99.211]) by smtp.googlemail.com with ESMTPSA id t81sm3848380wmg.6.2020.02.07.07.49.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Feb 2020 07:49:46 -0800 (PST) Subject: Re: [PATCH] Add support for a helper with 7 arguments To: Taylor Simpson , Richard Henderson , "qemu-devel@nongnu.org" References: <1580942510-2820-1-git-send-email-tsimpson@quicinc.com> From: Richard Henderson Autocrypt: addr=rth@twiddle.net; prefer-encrypt=mutual; keydata= mQENBFGuLC8BCADcAoWcnW9lTsDMzbO3MBU+KbiGaj5JPatEUscRDkQYM2fyNjJp2tIWDK5a n4yngeXB3eX61WbYR3QraRK8mlYLGxyAdHMEQfPipbqf3TmN043fssT2bc82ApJcs1zvLYgI rhMht7Dck7A0wNC1jo+ZjVVFig5gDTN7gOzaAdBtV8tVNUddwkLzzaGpfihhSD6U46NdqKOG Wlnn6TrkMy0QGdQ5NaXHkRlUjnnUTSW/nKfoxD+EI+A9V4sYOd8mc/TL4aJh/i/AiU57eLbo n17uQI6/VTWDUWl8USiz4x9c8vmqlywLx00tAFxxoRWqk4KVJlj+Sh0up/D/sJ+vPpgBABEB AAG0I1JpY2hhcmQgSGVuZGVyc29uIDxydGhAdHdpZGRsZS5uZXQ+iQFYBBMBAgBCAhsDBgsJ CAcDAgYVCAIJCgsEFgIDAQIeAQIXgAIZARYhBJyxjdr46EmtKvwWpK0ScMxN0CebBQJdweUY BQkP1h/pAAoJEK0ScMxN0CebqDsH/0YyfnXk+Dc++H37VCEKgRet2i1ATFzxRnifkvmdxha0 V+PVptQ2fwSe+w3KxoFecD8W75nysmUjrU/FicW9yU5YRlGONPZjruG02/KzmhA5PzWJdYO3 i/t0qRayvWIcX2qA/flsXEbmb/BbAFM05LQIdcOu74eiBFe5CBCOWBDJeneE1urIE0hSYxoh nCcG60ULrNj13ohZ4zAEluoY32qIo7/OPWmtR88cPrEbZT8k+RqgZbsotzaPT1/RlL74fL8k ofYfTgKAFH7eEy6fF2nzDp2GThVn+3sA62xtpSXUf/X1m75B40KOcq1EQbHypNTmBc1wt13e ibhPNEVX2am5AQ0EUa4sLwEIALITHfH3gciRNfQIe7awDTDvn6H3C6gDyCAnv5LiuLTLZiyK NZp3lNO3rPowyKrGT2RIDlumlqPgdeHzqEEX91YK0yk2vdFvwU04rJ4D+qRgdUPoeICLD1zo PwOv2FaY6Tf8dKYas1RHF5QU5yQNey8j7IYYoE2yGPn2PtBmvtmK4iLataUEvx0U385Zr+jf HscqwTiToryeDC8Io/9BsMvAssE5Yf5URS2nJ7LFOvc4njsQJPF1i9egBXaIloqv7p2hVCKJ Hl5UWIxitQ9QQIl6iU4LCpz8mVYTXwv48IAVpbUf7+ak9V9Kk3jCeQnlxCJBUHjUhoIzinbS JHPHtkkAEQEAAYkBPAQYAQIAJgIbDBYhBJyxjdr46EmtKvwWpK0ScMxN0CebBQJdweVIBQkP 1iAZAAoJEK0ScMxN0CebGHUH/RtouOlWl6To97tQsTJUq/2YwmRpFOsvV0/zCX4fKBGAbeZi VaELSt2+3UEErA+n8HwbQmjJ6IrdhA9GustOpOyCcbLVSMwql/OlAwBtDzCcC8dTU4zcuY2a rGG2A8i5krU85G9r1wowVcWZBsdmW7/dKiNoadLQiig4bHNiSaV4ograas5efyEjqTxiY+yG hzPw5DK2kbp2co8iDF1vW0LWPeLFBinCgItcI9LvgHWaB3rwjOfvNpMn5m64SoQYHB8wbnid erAjOzkBzmqnfS1tAUr8mtESStEwrEmNv0ZoA6S0Wt+c9pyTr+BpG4OFlhj7ZI+Eh7zOrr33 q9OBIdA= Message-ID: Date: Fri, 7 Feb 2020 15:49:44 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/7/20 12:43 PM, Taylor Simpson wrote: > >> -----Original Message----- >> From: Richard Henderson >> >> But I encourage you to re-think your purely mechanical approach to the >> hexagon port. It seems to me that you should be doing much more during >> the translation phase so that you can minimize the number of helpers that >> you require. > > There are a couple of things we could do > - Short term: Add #ifdef's to the generated code so that the helper isn't > compiled when there is a fWRAP_ defined. There are currently ~500 > instructions where this is the case. Definitely. > - Long term: Integrate rev.ng's approach that uses flex/bison to parse the > semantics and generate TCG code. There is perhaps an intermediate step that merely special-cases the load/store insns. With rare exceptions (hah!) these are the cases that will most often raise an exception. Moreover, they are the *only* cases that can raise an exception without requiring a helper call anyway. There are a number of cases that I can think of: { r6 = memb(r1) r7 = memb(r2) } qemu_ld t0, r1, MO_UB, mmu_idx qemu_ld t1, r2, MO_UB, mmu_idx mov r6, t0 mov r7, t1 { r6 = memb(r1) memb(r2) = r7 } qemu_ld t0, r1, MO_UB, mmu_idx qemu_st r7, r2, MO_UB, mmu_idx mov r6, t0 These being the "normal" case wherein the memops are unconditional, and can simply use a temp for semantics. Similarly for MEMOP, NV, or SYSTEM insns in slot0. { r6 = memb(r1) if (p0) r7 = memb(r7) } qemu_ld l0, r1, MO_UB, mmu_idx andi t1, p0, 1 brcondi t1, 0, L1 qemu_ld r7, r2, MO_UB, mmu_idx L1: mov r6, l0 For a conditional load in slot 0, we can load directly into the final destination register and skip the temporary. Because TCG doesn't do global register allocation, any temporary crossing a basic block boundary gets flushed to stack. So this avoids sending the r7 value through an unnecessary round trip. This works because (obviously) nothing can raise an exception after slot0, and the only thing that comes after is the commit phase. This can be extended to a conditional load in slot1, when we notice that the insn in slot0 cannot raise an exception. { memb(r1) = r3 memb(r2) = r4 } call helper_probe_access, r1, MMU_DATA_STORE, 1 call helper_probe_access, r2, MMU_DATA_STORE, 1 qemu_st r3, r1, MO_UB, mmu_idx qemu_st r4, r2, MO_UB, mmu_idx { memb(r1) = r3 r4 = memb(r2) } call helper_probe_access, r1, MMU_DATA_STORE, 1 call helper_probe_access, r2, MMU_DATA_LOAD, 1 qemu_st r3, r1, MO_UB, mmu_idx qemu_ld r4, r2, MO_UB, mmu_idx These cases with a store in slot1 are irritating, because I see that (1) all exceptions must be recognized before anything commits, and (2) slot1 exceptions must have preference over slot0 exceptions. But we can probe them easily enough. > - Long long term: A much more general approach will be to turn the C > semantics code into LLVM IR and generate TCG from the IR. Why would you imagine this to be more interesting than using flex/bison? r~