From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0O53-0001kD-OV for qemu-devel@nongnu.org; Tue, 18 Apr 2017 04:01:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0O50-0000ZC-Fp for qemu-devel@nongnu.org; Tue, 18 Apr 2017 04:01:45 -0400 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:34160) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d0O50-0000YG-8M for qemu-devel@nongnu.org; Tue, 18 Apr 2017 04:01:42 -0400 Received: by mail-wr0-x241.google.com with SMTP id u18so23598170wrc.1 for ; Tue, 18 Apr 2017 01:01:42 -0700 (PDT) Sender: Richard Henderson References: From: Richard Henderson Message-ID: Date: Tue, 18 Apr 2017 01:01:37 -0700 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/7] target/openrisc: add numcores and coreid support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stafford Horne , qemu-devel@nongnu.org Cc: openrisc@lists.librecores.org On 04/16/2017 04:23 PM, Stafford Horne wrote: > These are used to identify the processor in SMP system. Their > definition has been defined in verilog cores but it not yet part of the > spec but it will be soon. > > The proposal for this is available: > https://openrisc.io/proposals/core-identifier-and-number-of-cores > > Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson r~