Re: [Qemu-devel] [PATCH v2 2/5] target/arm: Restrict pre-ARMv7 cpus to TCG

[Thomas Huth <thuth@redhat.com>]

On 03/09/2019 13.47, Philippe Mathieu-Daudé wrote:
> KVM requires a cpu based on (at least) the ARMv7 architecture.
> 
> The following CPUs are disabled:
> 
> * ARMv4
> 
>   - StrongARM (SA1100/1110)
>   - OMAP1510 (TI925T)
> 
> * ARMv5
> 
>   - ARM926
>   - ARM946
>   - ARM1026
>   - XScale (PXA250/255/260/261/262/270)
> 
> * ARMv6
> 
>   - ARM1136
>   - ARM1176
>   - ARM11MPCore
>   - Cortex-M0
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> v2: fixed misplaced #endif (rth), list cpus
> ---
>  target/arm/cpu.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 2399c14471..f69780147c 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1678,6 +1678,8 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>  
> +#ifdef CONFIG_TCG
> +
>  static void arm926_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -1900,6 +1902,8 @@ static void cortex_m0_initfn(Object *obj)
>      cpu->midr = 0x410cc200;
>  }
>  
> +#endif
> +
>  static void cortex_m3_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -2283,6 +2287,8 @@ static void cortex_a15_initfn(Object *obj)
>      define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
>  }
>  
> +#ifdef CONFIG_TCG
> +
>  static void ti925t_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -2451,6 +2457,8 @@ static void pxa270c5_initfn(Object *obj)
>      cpu->reset_sctlr = 0x00000078;
>  }
>  
> +#endif
> +
>  #ifndef TARGET_AARCH64
>  /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
>   * otherwise, a CPU with as many features enabled as our emulation supports.
> @@ -2523,6 +2531,7 @@ struct ARMCPUInfo {
>  
>  static const ARMCPUInfo arm_cpus[] = {
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
> +#ifdef CONFIG_TCG
>      { .name = "arm926",      .initfn = arm926_initfn },
>      { .name = "arm946",      .initfn = arm946_initfn },
>      { .name = "arm1026",     .initfn = arm1026_initfn },
> @@ -2536,6 +2545,7 @@ static const ARMCPUInfo arm_cpus[] = {
>      { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
>      { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
>                               .class_init = arm_v7m_class_init },
> +#endif
>      { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
>                               .class_init = arm_v7m_class_init },
>      { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
> @@ -2548,6 +2558,7 @@ static const ARMCPUInfo arm_cpus[] = {
>      { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
>      { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
>      { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
> +#ifdef CONFIG_TCG
>      { .name = "ti925t",      .initfn = ti925t_initfn },
>      { .name = "sa1100",      .initfn = sa1100_initfn },
>      { .name = "sa1110",      .initfn = sa1110_initfn },
> @@ -2564,6 +2575,7 @@ static const ARMCPUInfo arm_cpus[] = {
>      { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
>      { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
>      { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
> +#endif
>  #ifndef TARGET_AARCH64
>      { .name = "max",         .initfn = arm_max_initfn },
>  #endif
> 

All that #ifdeffery is a little bit ugly. I wonder whether we could
solve this by moving the CPU registrations to separate files which then
only get compiled if the corresponding CONFIG_ARM_Vx switch is set.

That reminds me of a patch series of mine where I tried to make the code
compilable without CONFIG_ARM_V7M ... unfortunately, I never found
enough spare time to finish and publish it... I'll have a try to see
whether I can rebase it and send it as an RFC or so.

 Thomas