* [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
@ 2023-02-10 12:38 Daniel Henrique Barboza
2023-02-10 12:54 ` Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2023-02-10 12:38 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza
We have a RISCVCPU *cpu pointer available at the start of the function.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ad8d82662c..3a9472a2ff 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -60,7 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
* which is not supported by GVEC. So we set vl_eq_vlmax flag to true
* only when maxsz >= 8 bytes.
*/
- uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
+ uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
uint32_t maxsz = vlmax << sew;
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
--
2.39.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
2023-02-10 12:38 [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Daniel Henrique Barboza
@ 2023-02-10 12:54 ` Philippe Mathieu-Daudé
2023-02-11 2:50 ` weiwei
2023-02-16 16:11 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-10 12:54 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-riscv, alistair.francis
On 10/2/23 13:38, Daniel Henrique Barboza wrote:
> We have a RISCVCPU *cpu pointer available at the start of the function.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
2023-02-10 12:38 [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Daniel Henrique Barboza
2023-02-10 12:54 ` Philippe Mathieu-Daudé
@ 2023-02-11 2:50 ` weiwei
2023-02-16 16:11 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: weiwei @ 2023-02-11 2:50 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, liweiwei
On 2023/2/10 20:38, Daniel Henrique Barboza wrote:
> We have a RISCVCPU *cpu pointer available at the start of the function.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index ad8d82662c..3a9472a2ff 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -60,7 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
> * only when maxsz >= 8 bytes.
> */
> - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
> + uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
> uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
> uint32_t maxsz = vlmax << sew;
> bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
2023-02-10 12:38 [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Daniel Henrique Barboza
2023-02-10 12:54 ` Philippe Mathieu-Daudé
2023-02-11 2:50 ` weiwei
@ 2023-02-16 16:11 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: Palmer Dabbelt @ 2023-02-16 16:11 UTC (permalink / raw)
To: dbarboza; +Cc: qemu-devel, qemu-riscv, Alistair Francis, dbarboza
On Fri, 10 Feb 2023 04:38:36 PST (-0800), dbarboza@ventanamicro.com wrote:
> We have a RISCVCPU *cpu pointer available at the start of the function.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index ad8d82662c..3a9472a2ff 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -60,7 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
> * only when maxsz >= 8 bytes.
> */
> - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
> + uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
> uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
> uint32_t maxsz = vlmax << sew;
> bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
Thanks, applied to riscv-to-apply.next
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-02-10 12:38 [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Daniel Henrique Barboza
2023-02-10 12:54 ` Philippe Mathieu-Daudé
2023-02-11 2:50 ` weiwei
2023-02-16 16:11 ` Palmer Dabbelt
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