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Wed, 16 Apr 2025 16:38:34 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c33fa7794sm20358185ad.156.2025.04.16.16.38.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Apr 2025 16:38:33 -0700 (PDT) Message-ID: Date: Wed, 16 Apr 2025 16:38:32 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 000/163] tcg: Convert to TCGOutOp structures To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> Content-Language: en-US From: Pierrick Bouvier Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250415192515.232910-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 4/15/25 12:22, Richard Henderson wrote: > v2: 20250107080112.1175095-1-richard.henderson@linaro.org > v3: 20250216231012.2808572-1-richard.henderson@linaro.org > > Since it has been 2 months, I don't recall specific changes from v3 to v4. > It's mostly application of r-b tags. There is one more patch, which I > believe was Phil asking for one patch to be split. > > Patches still requiring review: 29, 41-43, 46, 47, 49-51, 55, 57, 59-62, > 64, 66-68, 70, 72-78, 80, 82-87, 89, 91, 93, 95, 97-102, 104, 106-162. > > > r~ > Thanks for this series Richard, reviewing this is a good opportunity to look at register allocation and associated constraints in tcg. The new way to define dynamic constraints is quite neat, and readable, as it was one of the feedback you previously asked. The only concern I have is that we could create silent "performance" related bugs, where a specific feature is deactivated because of a bad combination, but it's inherent to this approach and not a blocker. Even though I reviewed this series, it's hard for me to review all the target specific implementations, as I don't have your expertise on such a wide range of architectures. As a more general question, how do you approach testing for a series like this one? I see two different challenges, as it touches the IR itself, and the various backends. - For the IR, I don't know how extensive our complete test suite is (regarding coverage of all existing TCG ops), but I guess there are some holes there. It would be interesting to generate coverage data once we can get a single binary in the future. - For the various backends: * Are you able to compile QEMU on all concerned hosts and run testing there? * Or do you cross compile and run binaries emulated? * Or another way I might ignore at the moment? Regards, Pierrick