From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NhWgl-0000pC-VF for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:44 -0500 Received: from [199.232.76.173] (port=53095 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NhWgk-0000oQ-5F for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:42 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NhWgg-0006oL-BX for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:41 -0500 Received: from are.twiddle.net ([75.149.56.221]:37886) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NhWge-0006ny-1V for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:37 -0500 Message-Id: In-Reply-To: References: From: Richard Henderson Date: Tue, 16 Feb 2010 14:15:28 -0800 Subject: [Qemu-devel] [PATCH 4/6] tcg: Optional target implementation of ORC. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 11 +++++++++++ tcg/tcg-opc.h | 6 ++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 447878d..6ae1760 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1715,20 +1715,31 @@ static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_orc_i32 + tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); +#else TCGv_i32 t0; t0 = tcg_temp_new_i32(); tcg_gen_not_i32(t0, arg2); tcg_gen_or_i32(ret, arg1, t0); tcg_temp_free_i32(t0); +#endif } static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_orc_i64 + tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); +#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32 + tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#else TCGv_i64 t0; t0 = tcg_temp_new_i64(); tcg_gen_not_i64(t0, arg2); tcg_gen_or_i64(ret, arg1, t0); tcg_temp_free_i64(t0); +#endif } static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 6d855a7..34cdba5 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -112,6 +112,9 @@ DEF2(neg_i32, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_andc_i32 DEF2(andc_i32, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_orc_i32 +DEF2(orc_i32, 1, 2, 0, 0) +#endif #if TCG_TARGET_REG_BITS == 64 DEF2(mov_i64, 1, 1, 0, 0) @@ -191,6 +194,9 @@ DEF2(neg_i64, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_andc_i64 DEF2(andc_i64, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_orc_i64 +DEF2(orc_i64, 1, 2, 0, 0) +#endif #endif /* QEMU specific */ -- 1.6.2.5