From: "Cédric Le Goater" <clg@kaod.org>
To: Ed Tanous <etanous@nvidia.com>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Steven Lee <steven_lee@aspeedtech.com>,
Joel Stanley <joel@jms.id.au>, Troy Lee <leetroy@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Jamin Lin <jamin_lin@aspeedtech.com>,
qemu-arm@nongnu.org
Subject: Re: [PATCH 2/4] hw/arm/aspeed: Add second SPI chip to Aspeed model
Date: Wed, 2 Jul 2025 09:00:20 +0200 [thread overview]
Message-ID: <a0dfcbf7-cc09-4fb8-bc3b-3d4060fce5e9@kaod.org> (raw)
In-Reply-To: <20250701203400.71677-3-etanous@nvidia.com>
On 7/1/25 22:33, Ed Tanous wrote:
> Aspeed2600 has two spi lanes; Add a new struct that can mount the
> second SPI.
>
> Signed-off-by: Ed Tanous <etanous@nvidia.com>
> ---
> hw/arm/aspeed.c | 2 ++
> include/hw/arm/aspeed.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index d0b333646e..3ef7f6c5b2 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine)
> aspeed_board_init_flashes(&bmc->soc->spi[0],
> bmc->spi_model ? bmc->spi_model : amc->spi_model,
> 1, amc->num_cs);
> + aspeed_board_init_flashes(&bmc->soc->spi[1],
> + amc->spi2_model, 1, amc->num_cs2);
> }
>
> if (machine->kernel_filename && sc->num_cpus > 1) {
> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index 973277bea6..6c36455656 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -35,7 +35,9 @@ struct AspeedMachineClass {
> uint32_t hw_strap2;
> const char *fmc_model;
> const char *spi_model;
> + const char *spi2_model;
> uint32_t num_cs;
> + uint32_t num_cs2;
> uint32_t macs_mask;
> void (*i2c_init)(AspeedMachineState *bmc);
> uint32_t uart_default;
Another way specifying backends for all SPI devices is to use -blockdev :
$ qemu-system-arm -M ast2600-evb \
-blockdev node-name=fmc0,driver=file,filename=/path/to/fmc0.img \
-device mx66u51235f,bus=ssi.0,cs=0x0,drive=fmc0 \
-blockdev node-name=fmc1,driver=file,filename=/path/to/fmc1.img \
-device mx66u51235f,bus=ssi.0,cs=0x1,drive=fmc1 \
-blockdev node-name=spi1,driver=file,filename=/path/to/spi1.img \
-device mx66u51235f,cs=0x0,bus=ssi.1,drive=spi1 \
-nographic -nodefaults
See https://www.qemu.org/docs/master/system/arm/aspeed.html.
Have you tried it ?
Thanks,
C.
next prev parent reply other threads:[~2025-07-02 7:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-01 20:33 [PATCH 0/4] Add support for gb200-bmc machine Ed Tanous
2025-07-01 20:33 ` [PATCH 1/4] hw/arm: Add PCA9554 to ARM target Ed Tanous
2025-07-02 6:47 ` Cédric Le Goater
2025-07-02 7:04 ` Philippe Mathieu-Daudé
2025-07-02 19:20 ` etanous via
2025-07-02 21:21 ` Cédric Le Goater
2025-07-02 19:18 ` etanous via
2025-07-01 20:33 ` [PATCH 2/4] hw/arm/aspeed: Add second SPI chip to Aspeed model Ed Tanous
2025-07-02 7:00 ` Cédric Le Goater [this message]
2025-07-02 19:27 ` etanous via
2025-07-02 21:23 ` Cédric Le Goater
2025-07-02 21:32 ` Cédric Le Goater
2025-07-01 20:33 ` [PATCH 3/4] docs: add support for gb200-bmc Ed Tanous
2025-07-02 6:49 ` Cédric Le Goater
2025-07-01 20:34 ` [PATCH 4/4] hw/arm/aspeed: Add GB200 BMC target Ed Tanous
2025-07-02 21:38 ` Cédric Le Goater
2025-07-02 22:04 ` Ed Tanous via
2025-07-02 7:00 ` [PATCH 0/4] Add support for gb200-bmc machine Cédric Le Goater
2025-07-02 19:31 ` etanous via
2025-07-02 21:25 ` Cédric Le Goater
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