From: Richard Henderson <richard.henderson@linaro.org>
To: Xiaojuan Yang <yangxiaojuan@loongson.cn>, qemu-devel@nongnu.org
Cc: gaosong@loongson.cn, maobibo@loongson.cn, mst@redhat.com,
imammedo@redhat.com, ani@anisinha.ca,
mark.cave-ayland@ilande.co.uk
Subject: Re: [PATCH v6 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
Date: Fri, 3 Jun 2022 09:39:24 -0700 [thread overview]
Message-ID: <a0fb6ef8-9f25-08e9-a80f-258224700b2d@linaro.org> (raw)
In-Reply-To: <20220601102509.985650-35-yangxiaojuan@loongson.cn>
On 6/1/22 03:25, Xiaojuan Yang wrote:
> +static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
> +{
> + LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> + unsigned long offset = addr & 0xffff;
> + uint32_t index, cpu, ret = 0;
> +
> + switch (offset) {
> + case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
> + index = (offset - EXTIOI_NODETYPE_START) >> 2;
> + ret = s->nodetype[index];
> + break;
> + case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
> + index = offset - EXTIOI_IPMAP_START;
> + ret = *(uint32_t *)&s->ipmap[index];
This...
> + break;
> + case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
> + index = (offset - EXTIOI_ENABLE_START) >> 2;
> + ret = s->enable[index];
> + break;
> + case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
> + index = (offset - EXTIOI_BOUNCE_START) >> 2;
> + ret = s->bounce[index];
> + break;
> + case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
> + index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
> + cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
> + ret = s->coreisr[cpu][index];
> + break;
> + case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
> + index = offset - EXTIOI_COREMAP_START;
> + ret = *(uint32_t *)&s->coremap[index];
... and this are points of concern. You can't simply re-interpret an array of uint8_t as
uint32_t without running into host endian issues.
I wonder why you've declared them as uint8_t at all? Both read and write use this cast.
Was this some attempt to avoid
s->coremap[index / 4]?
or what?
> +static const VMStateDescription vmstate_loongarch_extioi = {
> + .name = TYPE_LOONGARCH_EXTIOI,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
> + VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, LOONGARCH_MAX_VCPUS,
> + EXTIOI_IRQS_GROUP_COUNT),
> + VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
> + EXTIOI_IRQS_NODETYPE_COUNT / 2),
> + VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
> + VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
> + VMSTATE_UINT8_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE),
> + VMSTATE_UINT8_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS),
> + VMSTATE_END_OF_LIST()
> + }
Missing the sw_* members.
r~
next prev parent reply other threads:[~2022-06-03 16:41 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-01 10:24 [PATCH v6 00/43] Add LoongArch softmmu support Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 01/43] target/loongarch: Add README Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 02/43] target/loongarch: Add core definition Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 03/43] target/loongarch: Add main translation routines Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 04/43] target/loongarch: Add fixed point arithmetic instruction translation Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 05/43] target/loongarch: Add fixed point shift " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 06/43] target/loongarch: Add fixed point bit " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 07/43] target/loongarch: Add fixed point load/store " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 08/43] target/loongarch: Add fixed point atomic " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 09/43] target/loongarch: Add fixed point extra " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 10/43] target/loongarch: Add floating point arithmetic " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 11/43] target/loongarch: Add floating point comparison " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 12/43] target/loongarch: Add floating point conversion " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 13/43] target/loongarch: Add floating point move " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 14/43] target/loongarch: Add floating point load/store " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 15/43] target/loongarch: Add branch " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 16/43] target/loongarch: Add disassembler Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 17/43] target/loongarch: Add target build suport Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 18/43] target/loongarch: Add system emulation introduction Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 19/43] target/loongarch: Add CSRs definition Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 20/43] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 21/43] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 22/43] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 23/43] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 24/43] target/loongarch: Add constant timer support Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 25/43] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 26/43] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 27/43] target/loongarch: Add TLB instruction support Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 28/43] target/loongarch: Add other core instructions support Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 29/43] target/loongarch: Add timer related " Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 30/43] hw/loongarch: Add support loongson3 virt machine type Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2022-06-01 10:24 ` [PATCH v6 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2022-06-01 10:25 ` [PATCH v6 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2022-06-03 16:39 ` Richard Henderson [this message]
2022-06-01 10:25 ` [PATCH v6 35/43] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2022-06-01 10:25 ` [PATCH v6 36/43] Enable common virtio pci support for LoongArch Xiaojuan Yang
2022-06-01 10:25 ` [PATCH v6 37/43] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2022-06-01 10:25 ` [PATCH v6 38/43] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2022-06-03 16:45 ` Richard Henderson
2022-06-01 10:25 ` [PATCH v6 39/43] hw/loongarch: Add LoongArch load elf function Xiaojuan Yang
2022-06-01 10:25 ` [PATCH v6 40/43] hw/loongarch: Add LoongArch power manager support Xiaojuan Yang
2022-06-03 16:49 ` Richard Henderson
2022-06-01 10:25 ` [PATCH v6 41/43] target/loongarch: Add gdb support Xiaojuan Yang
2022-06-01 10:25 ` [PATCH v6 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
2022-06-01 10:25 ` [PATCH v6 43/43] target/loongarch: 'make check-tcg' support Xiaojuan Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a0fb6ef8-9f25-08e9-a80f-258224700b2d@linaro.org \
--to=richard.henderson@linaro.org \
--cc=ani@anisinha.ca \
--cc=gaosong@loongson.cn \
--cc=imammedo@redhat.com \
--cc=maobibo@loongson.cn \
--cc=mark.cave-ayland@ilande.co.uk \
--cc=mst@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=yangxiaojuan@loongson.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).