From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PULL 00/60] accel/tcg patch queue
Date: Tue, 2 Nov 2021 15:11:44 -0400 [thread overview]
Message-ID: <a155ebce-e2ec-974f-355c-6bca26b22c80@linaro.org> (raw)
In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org>
On 11/2/21 7:06 AM, Richard Henderson wrote:
> The following changes since commit dd61b91c080cdfba1360a5ea1e4693fffb3445b0:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-29' into staging (2021-10-29 19:42:36 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211102
>
> for you to fetch changes up to 742f07628c0a0bd847b47ee0a0b20c44531e0ba5:
>
> linux-user: Handle BUS_ADRALN in host_signal_handler (2021-11-02 07:00:52 -0400)
>
> ----------------------------------------------------------------
> - Split out host signal handing from accel/tcg/user-exec.c
> to linux-user/host/arch/host-signal.h
> - Replace TCGCPUOps.tlb_fill with TCGCPUOps.record_sigsegv for user-only
> - Add TCGCPUOps.record_sigbus for user-only
> - Remove a lot of target-specific cpu_loop handling for signals,
> now accomplished with generic code.
>
> ----------------------------------------------------------------
> Richard Henderson (60):
> accel/tcg: Split out adjust_signal_pc
> accel/tcg: Move clear_helper_retaddr to cpu loop
> accel/tcg: Split out handle_sigsegv_accerr_write
> accel/tcg: Fold cpu_exit_tb_from_sighandler into caller
> configure: Merge riscv32 and riscv64 host architectures
> linux-user: Reorg handling for SIGSEGV
> linux-user/host/x86: Populate host_signal.h
> linux-user/host/ppc: Populate host_signal.h
> linux-user/host/alpha: Populate host_signal.h
> linux-user/host/sparc: Populate host_signal.h
> linux-user/host/arm: Populate host_signal.h
> linux-user/host/aarch64: Populate host_signal.h
> linux-user/host/s390: Populate host_signal.h
> linux-user/host/mips: Populate host_signal.h
> linux-user/host/riscv: Populate host_signal.h
> target/arm: Fixup comment re handle_cpu_signal
> linux-user/host/riscv: Improve host_signal_write
> linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER
> hw/core: Add TCGCPUOps.record_sigsegv
> linux-user: Add cpu_loop_exit_sigsegv
> target/alpha: Implement alpha_cpu_record_sigsegv
> target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup
> target/arm: Implement arm_cpu_record_sigsegv
> target/cris: Make cris_cpu_tlb_fill sysemu only
> target/hexagon: Remove hexagon_cpu_tlb_fill
> target/hppa: Make hppa_cpu_tlb_fill sysemu only
> target/i386: Implement x86_cpu_record_sigsegv
> target/m68k: Make m68k_cpu_tlb_fill sysemu only
> target/microblaze: Make mb_cpu_tlb_fill sysemu only
> target/mips: Make mips_cpu_tlb_fill sysemu only
> target/nios2: Implement nios2_cpu_record_sigsegv
> linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE
> target/openrisc: Make openrisc_cpu_tlb_fill sysemu only
> target/ppc: Implement ppc_cpu_record_sigsegv
> target/riscv: Make riscv_cpu_tlb_fill sysemu only
> target/s390x: Use probe_access_flags in s390_probe_access
> target/s390x: Implement s390_cpu_record_sigsegv
> target/sh4: Make sh4_cpu_tlb_fill sysemu only
> target/sparc: Make sparc_cpu_tlb_fill sysemu only
> target/xtensa: Make xtensa_cpu_tlb_fill sysemu only
> accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu
> hw/core: Add TCGCPUOps.record_sigbus
> linux-user: Add cpu_loop_exit_sigbus
> target/alpha: Implement alpha_cpu_record_sigbus
> target/arm: Implement arm_cpu_record_sigbus
> linux-user/hppa: Remove EXCP_UNALIGN handling
> target/microblaze: Do not set MO_ALIGN for user-only
> target/ppc: Move SPR_DSISR setting to powerpc_excp
> target/ppc: Set fault address in ppc_cpu_do_unaligned_access
> target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu
> linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling
> target/s390x: Implement s390x_cpu_record_sigbus
> target/sh4: Set fault address in superh_cpu_do_unaligned_access
> target/sparc: Remove DEBUG_UNALIGNED
> target/sparc: Split out build_sfsr
> target/sparc: Set fault address in sparc_cpu_do_unaligned_access
> accel/tcg: Report unaligned atomics for user-only
> accel/tcg: Report unaligned load/store for user-only
> tcg: Add helper_unaligned_{ld,st} for user-only sigbus
> linux-user: Handle BUS_ADRALN in host_signal_handler
>
> configure | 8 +-
> meson.build | 4 +-
> include/exec/exec-all.h | 55 +-
> include/hw/core/tcg-cpu-ops.h | 71 +-
> include/tcg/tcg-ldst.h | 5 +
> linux-user/host/aarch64/host-signal.h | 74 ++
> linux-user/host/alpha/host-signal.h | 42 +
> linux-user/host/arm/host-signal.h | 30 +
> linux-user/host/i386/host-signal.h | 25 +
> linux-user/host/mips/host-signal.h | 62 ++
> linux-user/host/ppc/host-signal.h | 25 +
> linux-user/host/ppc64/host-signal.h | 1 +
> linux-user/host/riscv/host-signal.h | 58 ++
> linux-user/host/{riscv64 => riscv}/hostdep.h | 4 +-
> linux-user/host/riscv32/hostdep.h | 11 -
> linux-user/host/s390/host-signal.h | 93 +++
> linux-user/host/s390x/host-signal.h | 1 +
> linux-user/host/sparc/host-signal.h | 54 ++
> linux-user/host/sparc64/host-signal.h | 1 +
> linux-user/host/x32/host-signal.h | 1 +
> linux-user/host/x86_64/host-signal.h | 24 +
> target/alpha/cpu.h | 21 +-
> target/arm/internals.h | 8 +
> target/cris/cpu.h | 8 +-
> target/hppa/cpu.h | 2 +-
> target/i386/tcg/helper-tcg.h | 6 +
> target/microblaze/cpu.h | 8 +-
> target/mips/tcg/tcg-internal.h | 7 +-
> target/nios2/cpu.h | 6 +
> target/openrisc/cpu.h | 7 +-
> target/ppc/cpu.h | 3 -
> target/ppc/internal.h | 17 +-
> target/s390x/s390x-internal.h | 9 +
> target/sh4/cpu.h | 6 +-
> target/xtensa/cpu.h | 2 +-
> accel/tcg/cpu-exec.c | 3 +-
> accel/tcg/user-exec.c | 861 +++------------------
> linux-user/aarch64/cpu_loop.c | 12 +-
> linux-user/alpha/cpu_loop.c | 15 -
> linux-user/arm/cpu_loop.c | 30 +-
> linux-user/cris/cpu_loop.c | 10 -
> linux-user/hexagon/cpu_loop.c | 24 +-
> linux-user/hppa/cpu_loop.c | 23 -
> linux-user/m68k/cpu_loop.c | 10 -
> linux-user/microblaze/cpu_loop.c | 10 -
> linux-user/mips/cpu_loop.c | 11 -
> linux-user/openrisc/cpu_loop.c | 25 +-
> linux-user/ppc/cpu_loop.c | 8 -
> linux-user/riscv/cpu_loop.c | 7 -
> linux-user/s390x/cpu_loop.c | 13 +-
> linux-user/sh4/cpu_loop.c | 8 -
> linux-user/signal.c | 133 +++-
> linux-user/sparc/cpu_loop.c | 25 -
> linux-user/xtensa/cpu_loop.c | 9 -
> target/alpha/cpu.c | 7 +-
> target/alpha/helper.c | 39 +-
> target/alpha/mem_helper.c | 30 +-
> target/arm/cpu.c | 7 +-
> target/arm/cpu_tcg.c | 7 +-
> target/arm/mte_helper.c | 6 +-
> target/arm/sve_helper.c | 2 +-
> target/arm/tlb_helper.c | 42 +-
> target/cris/cpu.c | 4 +-
> target/cris/helper.c | 18 -
> target/hexagon/cpu.c | 23 -
> target/hppa/cpu.c | 2 +-
> target/hppa/mem_helper.c | 15 -
> target/i386/tcg/tcg-cpu.c | 3 +-
> target/i386/tcg/user/excp_helper.c | 23 +-
> target/m68k/cpu.c | 2 +-
> target/m68k/helper.c | 6 +-
> target/microblaze/cpu.c | 2 +-
> target/microblaze/helper.c | 13 +-
> target/microblaze/translate.c | 16 +
> target/mips/cpu.c | 2 +-
> target/mips/tcg/user/tlb_helper.c | 59 --
> target/nios2/cpu.c | 6 +-
> target/nios2/helper.c | 7 +-
> target/openrisc/cpu.c | 2 +-
> target/openrisc/mmu.c | 9 -
> target/ppc/cpu_init.c | 6 +-
> target/ppc/excp_helper.c | 41 +-
> target/ppc/user_only_helper.c | 15 +-
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 21 +-
> target/s390x/cpu.c | 7 +-
> target/s390x/tcg/excp_helper.c | 45 +-
> target/s390x/tcg/mem_helper.c | 18 +-
> target/sh4/cpu.c | 2 +-
> target/sh4/helper.c | 9 +-
> target/sh4/op_helper.c | 5 +
> target/sparc/cpu.c | 2 +-
> target/sparc/ldst_helper.c | 22 -
> target/sparc/mmu_helper.c | 115 +--
> target/xtensa/cpu.c | 2 +-
> target/xtensa/helper.c | 22 +-
> .../host/{riscv64 => riscv}/safe-syscall.inc.S | 0
> target/cris/meson.build | 7 +-
> target/hppa/meson.build | 6 +-
> target/mips/tcg/meson.build | 3 -
> target/mips/tcg/user/meson.build | 3 -
> target/openrisc/meson.build | 2 +-
> target/sparc/meson.build | 2 +-
> 103 files changed, 1269 insertions(+), 1436 deletions(-)
> create mode 100644 linux-user/host/aarch64/host-signal.h
> create mode 100644 linux-user/host/alpha/host-signal.h
> create mode 100644 linux-user/host/arm/host-signal.h
> create mode 100644 linux-user/host/i386/host-signal.h
> create mode 100644 linux-user/host/mips/host-signal.h
> create mode 100644 linux-user/host/ppc/host-signal.h
> create mode 100644 linux-user/host/ppc64/host-signal.h
> create mode 100644 linux-user/host/riscv/host-signal.h
> rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%)
> delete mode 100644 linux-user/host/riscv32/hostdep.h
> create mode 100644 linux-user/host/s390/host-signal.h
> create mode 100644 linux-user/host/s390x/host-signal.h
> create mode 100644 linux-user/host/sparc/host-signal.h
> create mode 100644 linux-user/host/sparc64/host-signal.h
> create mode 100644 linux-user/host/x32/host-signal.h
> create mode 100644 linux-user/host/x86_64/host-signal.h
> delete mode 100644 target/mips/tcg/user/tlb_helper.c
> rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%)
> delete mode 100644 target/mips/tcg/user/meson.build
Applied, thanks.
r~
next prev parent reply other threads:[~2021-11-02 19:12 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 11:06 [PULL 00/60] accel/tcg patch queue Richard Henderson
2021-11-02 11:06 ` [PULL 01/60] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-11-02 11:06 ` [PULL 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-11-02 11:06 ` [PULL 03/60] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-11-02 11:06 ` [PULL 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-11-02 11:06 ` [PULL 05/60] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-11-02 11:06 ` [PULL 06/60] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-11-02 11:06 ` [PULL 07/60] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-11-02 11:06 ` [PULL 08/60] linux-user/host/ppc: " Richard Henderson
2021-11-02 11:06 ` [PULL 09/60] linux-user/host/alpha: " Richard Henderson
2021-11-02 11:06 ` [PULL 10/60] linux-user/host/sparc: " Richard Henderson
2021-11-02 11:06 ` [PULL 11/60] linux-user/host/arm: " Richard Henderson
2021-11-02 11:06 ` [PULL 12/60] linux-user/host/aarch64: " Richard Henderson
2021-11-02 11:06 ` [PULL 13/60] linux-user/host/s390: " Richard Henderson
2021-11-02 11:06 ` [PULL 14/60] linux-user/host/mips: " Richard Henderson
2021-11-02 11:06 ` [PULL 15/60] linux-user/host/riscv: " Richard Henderson
2021-11-02 11:06 ` [PULL 16/60] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-11-02 11:06 ` [PULL 17/60] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-11-02 11:06 ` [PULL 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-11-02 11:06 ` [PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 20/60] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 21/60] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-11-02 11:07 ` [PULL 23/60] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-11-02 11:07 ` [PULL 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 27/60] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 29/60] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 30/60] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 31/60] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-11-02 11:07 ` [PULL 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 34/60] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 36/60] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-11-02 11:07 ` [PULL 37/60] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 39/60] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 40/60] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-11-02 11:07 ` [PULL 42/60] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 43/60] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 44/60] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 45/60] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-11-02 11:07 ` [PULL 47/60] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-11-02 11:07 ` [PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-11-02 11:07 ` [PULL 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-11-02 11:07 ` [PULL 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-11-02 11:07 ` [PULL 52/60] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 53/60] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 54/60] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-11-02 11:07 ` [PULL 55/60] target/sparc: Split out build_sfsr Richard Henderson
2021-11-02 11:07 ` [PULL 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 57/60] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-11-02 11:07 ` [PULL 58/60] accel/tcg: Report unaligned load/store " Richard Henderson
2021-11-02 11:07 ` [PULL 59/60] tcg: Add helper_unaligned_{ld,st} for user-only sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 60/60] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
2021-11-02 19:11 ` Richard Henderson [this message]
2021-11-02 23:27 ` [PULL 00/60] accel/tcg patch queue Warner Losh
2021-11-02 23:35 ` Richard Henderson
2021-11-02 23:37 ` Warner Losh
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