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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde84be6sm25691f8f.48.2024.07.08.08.06.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jul 2024 08:06:27 -0700 (PDT) Message-ID: Date: Mon, 8 Jul 2024 17:06:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 10/19] hw/arm/smmu-common: Add support for nested TLB Content-Language: en-US To: Mostafa Saleh , qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org References: <20240701110241.2005222-1-smostafa@google.com> <20240701110241.2005222-11-smostafa@google.com> From: Eric Auger In-Reply-To: <20240701110241.2005222-11-smostafa@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.142, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/1/24 13:02, Mostafa Saleh wrote: > This patch adds support for nested (combined) TLB entries. > The main function combine_tlb() is not used here but in the next > patches, but to simplify the patches it is introduced first. > > Main changes: > 1) New field added in the SMMUTLBEntry struct: parent_perm, for > nested TLB, holds the stage-2 permission, this can be used to know > the origin of a permission fault from a cached entry as caching > the “and” of the permissions loses this information. > > SMMUPTWEventInfo is used to hold information about PTW faults so > the event can be populated, the value of stage used to be set > based on the current stage for TLB permission faults, however > with the parent_perm, it is now set based on which perm has > the missing permission > > When nesting is not enabled it has the same value as perm which > doesn't change the logic. > > 2) As combined TLB implementation is used, the combination logic > chooses: > - tg and level from the entry which has the smallest addr_mask. > - Based on that the iova that would be cached is recalculated. > - Translated_addr is chosen from stage-2. > > Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Eric > --- > hw/arm/smmu-common.c | 37 ++++++++++++++++++++++++++++++++---- > include/hw/arm/smmu-common.h | 1 + > 2 files changed, 34 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c > index 0840b5cffd..24b7d09e2b 100644 > --- a/hw/arm/smmu-common.c > +++ b/hw/arm/smmu-common.c > @@ -426,7 +426,8 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, > tlbe->entry.translated_addr = gpa; > tlbe->entry.iova = iova & ~mask; > tlbe->entry.addr_mask = mask; > - tlbe->entry.perm = PTE_AP_TO_PERM(ap); > + tlbe->parent_perm = PTE_AP_TO_PERM(ap); > + tlbe->entry.perm = tlbe->parent_perm; > tlbe->level = level; > tlbe->granule = granule_sz; > return 0; > @@ -547,7 +548,8 @@ static int smmu_ptw_64_s2(SMMUTransCfg *cfg, > tlbe->entry.translated_addr = gpa; > tlbe->entry.iova = ipa & ~mask; > tlbe->entry.addr_mask = mask; > - tlbe->entry.perm = s2ap; > + tlbe->parent_perm = s2ap; > + tlbe->entry.perm = tlbe->parent_perm; > tlbe->level = level; > tlbe->granule = granule_sz; > return 0; > @@ -562,6 +564,30 @@ error: > return -EINVAL; > } > > +/* > + * combine S1 and S2 TLB entries into a single entry. > + * As a result the S1 entry is overriden with combined data. > + */ > +static void __attribute__((unused)) combine_tlb(SMMUTLBEntry *tlbe, > + SMMUTLBEntry *tlbe_s2, > + dma_addr_t iova, > + SMMUTransCfg *cfg) > +{ > + if (tlbe_s2->entry.addr_mask < tlbe->entry.addr_mask) { > + tlbe->entry.addr_mask = tlbe_s2->entry.addr_mask; > + tlbe->granule = tlbe_s2->granule; > + tlbe->level = tlbe_s2->level; > + } > + > + tlbe->entry.translated_addr = CACHED_ENTRY_TO_ADDR(tlbe_s2, > + tlbe->entry.translated_addr); > + > + tlbe->entry.iova = iova & ~tlbe->entry.addr_mask; > + /* parent_perm has s2 perm while perm keeps s1 perm. */ > + tlbe->parent_perm = tlbe_s2->entry.perm; > + return; > +} > + > /** > * smmu_ptw - Walk the page tables for an IOVA, according to @cfg > * > @@ -639,9 +665,12 @@ SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTransCfg *cfg, dma_addr_t addr, > > cached_entry = smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr); > if (cached_entry) { > - if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { > + if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & > + cached_entry->parent_perm & IOMMU_WO)) { > info->type = SMMU_PTW_ERR_PERMISSION; > - info->stage = cfg->stage; > + info->stage = !(cached_entry->entry.perm & IOMMU_WO) ? > + SMMU_STAGE_1 : > + SMMU_STAGE_2; > return NULL; > } > return cached_entry; > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index 09d3b9e734..1db566d451 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -77,6 +77,7 @@ typedef struct SMMUTLBEntry { > IOMMUTLBEntry entry; > uint8_t level; > uint8_t granule; > + IOMMUAccessFlags parent_perm; > } SMMUTLBEntry; > > /* Stage-2 configuration. */