From: Jiajie Chen <c@jia.je>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: gaosong@loongson.cn, git@xen0n.name
Subject: Re: [PATCH 0/5] Add LoongArch v1.1 instructions
Date: Thu, 26 Oct 2023 01:13:55 +0800 [thread overview]
Message-ID: <a1784c3c-b00e-4cb6-a262-96e6cbaa5c30@jia.je> (raw)
In-Reply-To: <1af667c0-f1ba-4538-9aec-8232397dd3c5@jia.je>
On 2023/10/24 14:10, Jiajie Chen wrote:
>
> On 2023/10/24 07:26, Richard Henderson wrote:
>> On 10/23/23 08:29, Jiajie Chen wrote:
>>> This patch series implements the new instructions except sc.q,
>>> because I do not know how to match a pair of ll.d to sc.q.
>>
>> There are a couple of examples within the tree.
>>
>> See target/arm/tcg/translate-a64.c, gen_store_exclusive, TCGv_i128
>> block.
>> See target/ppc/translate.c, gen_stqcx_.
>
>
> The situation here is slightly different: aarch64 and ppc64 have both
> 128-bit ll and sc, however LoongArch v1.1 only has 64-bit ll and
> 128-bit sc. I guest the intended usage of sc.q is:
>
>
> ll.d lo, base, 0
>
> ll.d hi, base, 4
>
> # do some computation
>
> sc.q lo, hi, base
>
> # try again if sc failed
Possibly use the combination of ll.d and ld.d:
ll.d lo, base, 0
ld.d hi, base, 4
# do some computation
sc.q lo, hi, base
# try again if sc failed
Then a possible implementation of gen_ll() would be: align base to
128-bit boundary, read 128-bit from memory, save 64-bit part to rd and
record whole 128-bit data in llval. Then, in gen_sc_q(), it uses a
128-bit cmpxchg.
But what about the reversed instruction pattern: ll.d hi, base, 4; ld.d
lo, base 0?
Since there are no existing code utilizing the new sc.q instruction, I
don't know what should we consider here.
>
>
>
>>
>>
>> r~
next prev parent reply other threads:[~2023-10-25 17:15 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 15:29 [PATCH 0/5] Add LoongArch v1.1 instructions Jiajie Chen
2023-10-23 15:29 ` [PATCH 1/5] include/exec/memop.h: Add MO_TESB Jiajie Chen
2023-10-23 15:49 ` David Hildenbrand
2023-10-23 15:52 ` Jiajie Chen
2023-10-23 15:29 ` [PATCH 2/5] target/loongarch: Add am{swap/add}[_db].{b/h} Jiajie Chen
2023-10-23 22:50 ` Richard Henderson
2023-10-23 15:29 ` [PATCH 3/5] target/loongarch: Add amcas[_db].{b/h/w/d} Jiajie Chen
2023-10-23 15:35 ` Jiajie Chen
2023-10-23 23:00 ` Richard Henderson
2023-10-23 22:59 ` Richard Henderson
2023-10-23 15:29 ` [PATCH 4/5] target/loongarch: Add estimated reciprocal instructions Jiajie Chen
2023-10-23 23:02 ` Richard Henderson
2023-10-23 15:29 ` [PATCH 5/5] target/loongarch: Add llacq/screl instructions Jiajie Chen
2023-10-23 23:19 ` Richard Henderson
2023-10-23 23:26 ` [PATCH 0/5] Add LoongArch v1.1 instructions Richard Henderson
2023-10-24 6:10 ` Jiajie Chen
2023-10-25 17:13 ` Jiajie Chen [this message]
2023-10-25 19:04 ` Richard Henderson
2023-10-26 1:38 ` Jiajie Chen
2023-10-26 6:54 ` gaosong
2023-10-28 13:09 ` Jiajie Chen
2023-10-30 8:23 ` gaosong
2023-10-30 11:54 ` Jiajie Chen
2023-10-31 9:11 ` gaosong
2023-10-31 9:13 ` Jiajie Chen
2023-10-31 11:06 ` gaosong
2023-10-31 11:10 ` Jiajie Chen
2023-10-31 12:12 ` gaosong
2025-11-10 3:42 ` gaosong
2025-11-10 16:00 ` Jiajie Chen
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