* [PATCH 01/25] m25p80: Improve error when the backend file size does not match the device
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 02/25] aspeed: Add Supermicro X11 SPI machine type Cédric Le Goater
` (23 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Cédric Le Goater,
Peter Delevoryas, Alistair Francis
Currently, when a block backend is attached to a m25p80 device and the
associated file size does not match the flash model, QEMU complains
with the error message "failed to read the initial flash content".
This is confusing for the user.
Use blk_check_size_and_read_all() instead of blk_pread() to improve
the reported error.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221115151000.2080833-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/block/m25p80.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 02adc87527..68a757abf3 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "sysemu/block-backend.h"
+#include "hw/block/block.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/ssi/ssi.h"
@@ -1614,8 +1615,7 @@ static void m25p80_realize(SSIPeripheral *ss, Error **errp)
trace_m25p80_binding(s);
s->storage = blk_blockalign(s->blk, s->size);
- if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
- error_setg(errp, "failed to read the initial flash content");
+ if (!blk_check_size_and_read_all(s->blk, s->storage, s->size, errp)) {
return;
}
} else {
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 02/25] aspeed: Add Supermicro X11 SPI machine type
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
2023-01-19 12:34 ` [PATCH 01/25] m25p80: Improve error when the backend file size does not match the device Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:39 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 03/25] hw/net: Fix read of uninitialized memory in ftgmac100 Cédric Le Goater
` (22 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Guenter Roeck,
Cédric Le Goater
From: Guenter Roeck <linux@roeck-us.net>
supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
the Supermicro documentation for X11 BMCs, and it does not match the
devicetree file in the Linux kernel.
As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
while others use AST2500.
Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC
to match the devicetree description in the Linux kernel. Hardware
configuration details for this machine type are guesswork and taken
from defaults as well as from the Linux kernel devicetree file.
The new machine type was tested with aspeed-bmc-supermicro-x11spi.dts
from the Linux kernel and with Linux versions 6.0.3 and 6.1-rc2.
Linux booted successfully from initrd and from both SPI interfaces.
Ethernet interfaces were confirmed to be operational.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20221025165109.1226001-1-linux@roeck-us.net
Message-Id: <20221025165109.1226001-1-linux@roeck-us.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 55f114ef72..4919a1fe9e 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -71,6 +71,16 @@ struct AspeedMachineState {
SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
+/* TODO: Find the actual hardware value */
+#define SUPERMICROX11_SPI_BMC_HW_STRAP1 ( \
+ AST2500_HW_STRAP1_DEFAULTS | \
+ SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
+ SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
+ SCU_AST2500_HW_STRAP_UART_DEBUG | \
+ SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
+ SCU_HW_STRAP_SPI_WIDTH | \
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
+
/* AST2500 evb hardware value: 0xF100C2E6 */
#define AST2500_EVB_HW_STRAP1 (( \
AST2500_HW_STRAP1_DEFAULTS | \
@@ -1141,6 +1151,25 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
mc->default_ram_size = 256 * MiB;
}
+static void aspeed_machine_supermicrox11_spi_bmc_class_init(ObjectClass *oc,
+ void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
+ amc->soc_name = "ast2500-a1";
+ amc->hw_strap1 = SUPERMICROX11_SPI_BMC_HW_STRAP1;
+ amc->fmc_model = "mx25l25635e";
+ amc->spi_model = "mx25l25635e";
+ amc->num_cs = 1;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+ amc->i2c_init = palmetto_bmc_i2c_init;
+ mc->default_ram_size = 512 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
+}
+
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1522,6 +1551,10 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("supermicrox11-spi-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_supermicrox11_spi_bmc_class_init,
}, {
.name = MACHINE_TYPE_NAME("ast2500-evb"),
.parent = TYPE_ASPEED_MACHINE,
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 02/25] aspeed: Add Supermicro X11 SPI machine type
2023-01-19 12:34 ` [PATCH 02/25] aspeed: Add Supermicro X11 SPI machine type Cédric Le Goater
@ 2023-02-01 5:39 ` Joel Stanley
2023-02-01 7:49 ` Cédric Le Goater
0 siblings, 1 reply; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:39 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé,
Guenter Roeck
On Thu, 19 Jan 2023 at 12:36, Cédric Le Goater <clg@kaod.org> wrote:
>
> From: Guenter Roeck <linux@roeck-us.net>
>
> supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
> the Supermicro documentation for X11 BMCs, and it does not match the
> devicetree file in the Linux kernel.
I found this sentence confusing; AFAICT X11 doesn't name a specific
motherboard. It appears to be a marketing term for a bunch of
different things.
> As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
> while others use AST2500.
>
> Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC
How about supermicro-x11spi-bmc? It would match the product name:
https://www.supermicro.com/en/products/motherboard/X11SPi-TF
as well as the device tree filename.
> to match the devicetree description in the Linux kernel. Hardware
> configuration details for this machine type are guesswork and taken
> from defaults as well as from the Linux kernel devicetree file.
>
> The new machine type was tested with aspeed-bmc-supermicro-x11spi.dts
> from the Linux kernel and with Linux versions 6.0.3 and 6.1-rc2.
> Linux booted successfully from initrd and from both SPI interfaces.
> Ethernet interfaces were confirmed to be operational.
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Link: https://lore.kernel.org/r/20221025165109.1226001-1-linux@roeck-us.net
> Message-Id: <20221025165109.1226001-1-linux@roeck-us.net>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/arm/aspeed.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 55f114ef72..4919a1fe9e 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -71,6 +71,16 @@ struct AspeedMachineState {
> SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
> SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
>
> +/* TODO: Find the actual hardware value */
> +#define SUPERMICROX11_SPI_BMC_HW_STRAP1 ( \
> + AST2500_HW_STRAP1_DEFAULTS | \
> + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
> + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
> + SCU_AST2500_HW_STRAP_UART_DEBUG | \
> + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
> + SCU_HW_STRAP_SPI_WIDTH | \
> + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
> +
> /* AST2500 evb hardware value: 0xF100C2E6 */
> #define AST2500_EVB_HW_STRAP1 (( \
> AST2500_HW_STRAP1_DEFAULTS | \
> @@ -1141,6 +1151,25 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
> mc->default_ram_size = 256 * MiB;
> }
>
> +static void aspeed_machine_supermicrox11_spi_bmc_class_init(ObjectClass *oc,
> + void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> +
> + mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
> + amc->soc_name = "ast2500-a1";
> + amc->hw_strap1 = SUPERMICROX11_SPI_BMC_HW_STRAP1;
> + amc->fmc_model = "mx25l25635e";
> + amc->spi_model = "mx25l25635e";
> + amc->num_cs = 1;
> + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> + amc->i2c_init = palmetto_bmc_i2c_init;
> + mc->default_ram_size = 512 * MiB;
> + mc->default_cpus = mc->min_cpus = mc->max_cpus =
> + aspeed_soc_num_cpus(amc->soc_name);
> +}
> +
> static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -1522,6 +1551,10 @@ static const TypeInfo aspeed_machine_types[] = {
> .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
> .parent = TYPE_ASPEED_MACHINE,
> .class_init = aspeed_machine_supermicrox11_bmc_class_init,
> + }, {
> + .name = MACHINE_TYPE_NAME("supermicrox11-spi-bmc"),
> + .parent = TYPE_ASPEED_MACHINE,
> + .class_init = aspeed_machine_supermicrox11_spi_bmc_class_init,
> }, {
> .name = MACHINE_TYPE_NAME("ast2500-evb"),
> .parent = TYPE_ASPEED_MACHINE,
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH 02/25] aspeed: Add Supermicro X11 SPI machine type
2023-02-01 5:39 ` Joel Stanley
@ 2023-02-01 7:49 ` Cédric Le Goater
2023-02-01 15:01 ` Guenter Roeck
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-02-01 7:49 UTC (permalink / raw)
To: Joel Stanley
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé,
Guenter Roeck
On 2/1/23 06:39, Joel Stanley wrote:
> On Thu, 19 Jan 2023 at 12:36, Cédric Le Goater <clg@kaod.org> wrote:
>>
>> From: Guenter Roeck <linux@roeck-us.net>
>>
>> supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
>> the Supermicro documentation for X11 BMCs, and it does not match the
>> devicetree file in the Linux kernel.
>
> I found this sentence confusing; AFAICT X11 doesn't name a specific
> motherboard. It appears to be a marketing term for a bunch of
> different things.
>
>> As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
>> while others use AST2500.
>>
>> Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC
>
> How about supermicro-x11spi-bmc? It would match the product name:
>
> https://www.supermicro.com/en/products/motherboard/X11SPi-TF
>
> as well as the device tree filename.
Indeed,
model = "X11SPI BMC";
compatible = "supermicro,x11spi-bmc", "aspeed,ast2500";
I was the one who suggested the name. Let's change if Guenter agrees.
Thanks,
C.
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH 02/25] aspeed: Add Supermicro X11 SPI machine type
2023-02-01 7:49 ` Cédric Le Goater
@ 2023-02-01 15:01 ` Guenter Roeck
0 siblings, 0 replies; 42+ messages in thread
From: Guenter Roeck @ 2023-02-01 15:01 UTC (permalink / raw)
To: Cédric Le Goater, Joel Stanley
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé
On 1/31/23 23:49, Cédric Le Goater wrote:
> On 2/1/23 06:39, Joel Stanley wrote:
>> On Thu, 19 Jan 2023 at 12:36, Cédric Le Goater <clg@kaod.org> wrote:
>>>
>>> From: Guenter Roeck <linux@roeck-us.net>
>>>
>>> supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
>>> the Supermicro documentation for X11 BMCs, and it does not match the
>>> devicetree file in the Linux kernel.
>>
>> I found this sentence confusing; AFAICT X11 doesn't name a specific
>> motherboard. It appears to be a marketing term for a bunch of
>> different things.
>>
>>> As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
>>> while others use AST2500.
>>>
>>> Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC
>>
>> How about supermicro-x11spi-bmc? It would match the product name:
>>
>> https://www.supermicro.com/en/products/motherboard/X11SPi-TF
>>
>> as well as the device tree filename.
>
> Indeed,
>
> model = "X11SPI BMC";
> compatible = "supermicro,x11spi-bmc", "aspeed,ast2500";
>
> I was the one who suggested the name. Let's change if Guenter agrees.
>
Sure, any name is fine with me.
Guenter
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/25] hw/net: Fix read of uninitialized memory in ftgmac100
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
2023-01-19 12:34 ` [PATCH 01/25] m25p80: Improve error when the backend file size does not match the device Cédric Le Goater
2023-01-19 12:34 ` [PATCH 02/25] aspeed: Add Supermicro X11 SPI machine type Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:41 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 04/25] avocado/boot_linux_console.py: Update ast2600 test Cédric Le Goater
` (21 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Stephen Longfield,
Hao Wu, Cédric Le Goater
From: Stephen Longfield <slongfield@google.com>
With the `size += 4` before the call to `crc32`, the CRC calculation
would overrun the buffer. Size is used in the while loop starting on
line 1009 to determine how much data to write back, with the last
four bytes coming from `crc_ptr`, so do need to increase it, but should
do this after the computation.
I'm unsure why this use of uninitialized memory in the CRC doesn't
result in CRC errors, but it seems clear to me that it should not be
included in the calculation.
Signed-off-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Message-Id: <20221220221437.3303721-1-slongfield@google.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/net/ftgmac100.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 83ef0a783e..d3bf14be53 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -980,9 +980,9 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
return size;
}
- /* 4 bytes for the CRC. */
- size += 4;
crc = cpu_to_be32(crc32(~0, buf, size));
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
+ size += 4;
crc_ptr = (uint8_t *) &crc;
/* Huge frames are truncated. */
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 03/25] hw/net: Fix read of uninitialized memory in ftgmac100
2023-01-19 12:34 ` [PATCH 03/25] hw/net: Fix read of uninitialized memory in ftgmac100 Cédric Le Goater
@ 2023-02-01 5:41 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:41 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé,
Stephen Longfield, Hao Wu
On Thu, 19 Jan 2023 at 12:39, Cédric Le Goater <clg@kaod.org> wrote:
>
> From: Stephen Longfield <slongfield@google.com>
>
> With the `size += 4` before the call to `crc32`, the CRC calculation
> would overrun the buffer. Size is used in the while loop starting on
> line 1009 to determine how much data to write back, with the last
> four bytes coming from `crc_ptr`, so do need to increase it, but should
> do this after the computation.
>
> I'm unsure why this use of uninitialized memory in the CRC doesn't
> result in CRC errors, but it seems clear to me that it should not be
> included in the calculation.
Does this affect the error counters observed under Linux?
>
> Signed-off-by: Stephen Longfield <slongfield@google.com>
> Reviewed-by: Hao Wu <wuhaotsh@google.com>
> Message-Id: <20221220221437.3303721-1-slongfield@google.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> hw/net/ftgmac100.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
> index 83ef0a783e..d3bf14be53 100644
> --- a/hw/net/ftgmac100.c
> +++ b/hw/net/ftgmac100.c
> @@ -980,9 +980,9 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
> return size;
> }
>
> - /* 4 bytes for the CRC. */
> - size += 4;
> crc = cpu_to_be32(crc32(~0, buf, size));
> + /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
> + size += 4;
> crc_ptr = (uint8_t *) &crc;
>
> /* Huge frames are truncated. */
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 04/25] avocado/boot_linux_console.py: Update ast2600 test
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (2 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 03/25] hw/net: Fix read of uninitialized memory in ftgmac100 Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:46 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 05/25] m25p80: Add the is25wp256 SFPD table Cédric Le Goater
` (20 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Joel Stanley,
Cédric Le Goater
From: Joel Stanley <joel@jms.id.au>
Update the test_arm_ast2600_debian test to
- the latest Debian kernel
- use the Rainier machine instead of Tacoma
Both of which contains support for more hardware and thus exercises more
of the hardware Qemu models.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220607011938.1676459-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/avocado/boot_linux_console.py | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index 8c1d981586..f3a1d00be9 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -1098,18 +1098,18 @@ def test_arm_vexpressa9(self):
def test_arm_ast2600_debian(self):
"""
:avocado: tags=arch:arm
- :avocado: tags=machine:tacoma-bmc
+ :avocado: tags=machine:rainier-bmc
"""
deb_url = ('http://snapshot.debian.org/archive/debian/'
- '20210302T203551Z/'
+ '20220606T211338Z/'
'pool/main/l/linux/'
- 'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb')
- deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e'
+ 'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
+ deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
algorithm='sha256')
- kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp')
+ kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
dtb_path = self.extract_from_deb(deb_path,
- '/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb')
+ '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
self.vm.set_console()
self.vm.add_args('-kernel', kernel_path,
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 04/25] avocado/boot_linux_console.py: Update ast2600 test
2023-01-19 12:34 ` [PATCH 04/25] avocado/boot_linux_console.py: Update ast2600 test Cédric Le Goater
@ 2023-02-01 5:46 ` Joel Stanley
2023-02-01 7:51 ` Cédric Le Goater
0 siblings, 1 reply; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:46 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé
On Thu, 19 Jan 2023 at 12:35, Cédric Le Goater <clg@kaod.org> wrote:
>
> From: Joel Stanley <joel@jms.id.au>
>
> Update the test_arm_ast2600_debian test to
>
> - the latest Debian kernel
Would you like a newer version of this patch that uses the latest kernel?
> - use the Rainier machine instead of Tacoma
>
> Both of which contains support for more hardware and thus exercises more
> of the hardware Qemu models.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20220607011938.1676459-1-joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> tests/avocado/boot_linux_console.py | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
> index 8c1d981586..f3a1d00be9 100644
> --- a/tests/avocado/boot_linux_console.py
> +++ b/tests/avocado/boot_linux_console.py
> @@ -1098,18 +1098,18 @@ def test_arm_vexpressa9(self):
> def test_arm_ast2600_debian(self):
> """
> :avocado: tags=arch:arm
> - :avocado: tags=machine:tacoma-bmc
> + :avocado: tags=machine:rainier-bmc
> """
> deb_url = ('http://snapshot.debian.org/archive/debian/'
> - '20210302T203551Z/'
> + '20220606T211338Z/'
> 'pool/main/l/linux/'
> - 'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb')
> - deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e'
> + 'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
> + deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
> deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
> algorithm='sha256')
> - kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp')
> + kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
> dtb_path = self.extract_from_deb(deb_path,
> - '/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb')
> + '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
>
> self.vm.set_console()
> self.vm.add_args('-kernel', kernel_path,
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH 04/25] avocado/boot_linux_console.py: Update ast2600 test
2023-02-01 5:46 ` Joel Stanley
@ 2023-02-01 7:51 ` Cédric Le Goater
0 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-02-01 7:51 UTC (permalink / raw)
To: Joel Stanley
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé
On 2/1/23 06:46, Joel Stanley wrote:
> On Thu, 19 Jan 2023 at 12:35, Cédric Le Goater <clg@kaod.org> wrote:
>>
>> From: Joel Stanley <joel@jms.id.au>
>>
>> Update the test_arm_ast2600_debian test to
>>
>> - the latest Debian kernel
>
> Would you like a newer version of this patch that uses the latest kernel?
Sure. We can not test all kernels. Using the latest is the best approach I think.
Thanks,
C.
>
>> - use the Rainier machine instead of Tacoma
>>
>> Both of which contains support for more hardware and thus exercises more
>> of the hardware Qemu models.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>> Message-Id: <20220607011938.1676459-1-joel@jms.id.au>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> tests/avocado/boot_linux_console.py | 12 ++++++------
>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
>> index 8c1d981586..f3a1d00be9 100644
>> --- a/tests/avocado/boot_linux_console.py
>> +++ b/tests/avocado/boot_linux_console.py
>> @@ -1098,18 +1098,18 @@ def test_arm_vexpressa9(self):
>> def test_arm_ast2600_debian(self):
>> """
>> :avocado: tags=arch:arm
>> - :avocado: tags=machine:tacoma-bmc
>> + :avocado: tags=machine:rainier-bmc
>> """
>> deb_url = ('http://snapshot.debian.org/archive/debian/'
>> - '20210302T203551Z/'
>> + '20220606T211338Z/'
>> 'pool/main/l/linux/'
>> - 'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb')
>> - deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e'
>> + 'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
>> + deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
>> deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
>> algorithm='sha256')
>> - kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp')
>> + kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
>> dtb_path = self.extract_from_deb(deb_path,
>> - '/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb')
>> + '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
>>
>> self.vm.set_console()
>> self.vm.add_args('-kernel', kernel_path,
>> --
>> 2.39.0
>>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 05/25] m25p80: Add the is25wp256 SFPD table
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (3 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 04/25] avocado/boot_linux_console.py: Update ast2600 test Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:40 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 06/25] tests/avocado/machine_aspeed.py: update buildroot tests Cédric Le Goater
` (19 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Guenter Roeck,
Michael Walle, Tudor Ambarus, Cédric Le Goater
From: Guenter Roeck <linux@roeck-us.net>
Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
Cc: Michael Walle <michael@walle.cc>
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221221122213.1458540-1-linux@roeck-us.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/block/m25p80_sfdp.h | 2 ++
hw/block/m25p80.c | 3 ++-
hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index df7adfb5ce..011a880f66 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -26,4 +26,6 @@ uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
+uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
+
#endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 68a757abf3..dc5ffbc4ff 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -222,7 +222,8 @@ static const FlashPartInfo known_devices[] = {
{ INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
{ INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
{ INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
- { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
+ { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K),
+ .sfdp_read = m25p80_sfdp_is25wp256 },
/* Macronix */
{ INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index 77615fa29e..b33811a4f5 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -330,3 +330,43 @@ static const uint8_t sfdp_w25q01jvq[] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
};
define_sfdp_read(w25q01jvq);
+
+/*
+ * Integrated Silicon Solution (ISSI)
+ */
+
+static const uint8_t sfdp_is25wp256[] = {
+ 0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+ 0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
+ 0x9d, 0x05, 0x01, 0x03, 0x80, 0x00, 0x00, 0x02,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xe5, 0x20, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x0f,
+ 0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x80, 0xbb,
+ 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+ 0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+ 0x10, 0xd8, 0x00, 0xff, 0x23, 0x4a, 0xc9, 0x00,
+ 0x82, 0xd8, 0x11, 0xce, 0xcc, 0xcd, 0x68, 0x46,
+ 0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xae, 0xd5, 0x5c,
+ 0x4a, 0x42, 0x2c, 0xff, 0xf0, 0x30, 0xfa, 0xa9,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0x50, 0x19, 0x50, 0x16, 0x9f, 0xf9, 0xc0, 0x64,
+ 0x8f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(is25wp256);
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 05/25] m25p80: Add the is25wp256 SFPD table
2023-01-19 12:34 ` [PATCH 05/25] m25p80: Add the is25wp256 SFPD table Cédric Le Goater
@ 2023-02-01 5:40 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:40 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé,
Guenter Roeck, Michael Walle, Tudor Ambarus
On Thu, 19 Jan 2023 at 12:36, Cédric Le Goater <clg@kaod.org> wrote:
>
> From: Guenter Roeck <linux@roeck-us.net>
>
> Generated from hardware using the following command and then padding
> with 0xff to fill out a power-of-2:
> xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
>
> Cc: Michael Walle <michael@walle.cc>
> Cc: Tudor Ambarus <tudor.ambarus@linaro.org>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20221221122213.1458540-1-linux@roeck-us.net>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
I wonder if we could update the code so the padding is assumed.
> ---
> hw/block/m25p80_sfdp.h | 2 ++
> hw/block/m25p80.c | 3 ++-
> hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 44 insertions(+), 1 deletion(-)
>
> diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
> index df7adfb5ce..011a880f66 100644
> --- a/hw/block/m25p80_sfdp.h
> +++ b/hw/block/m25p80_sfdp.h
> @@ -26,4 +26,6 @@ uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
>
> uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
>
> +uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
> +
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 68a757abf3..dc5ffbc4ff 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -222,7 +222,8 @@ static const FlashPartInfo known_devices[] = {
> { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
> { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
> { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
> - { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
> + { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K),
> + .sfdp_read = m25p80_sfdp_is25wp256 },
>
> /* Macronix */
> { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
> diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
> index 77615fa29e..b33811a4f5 100644
> --- a/hw/block/m25p80_sfdp.c
> +++ b/hw/block/m25p80_sfdp.c
> @@ -330,3 +330,43 @@ static const uint8_t sfdp_w25q01jvq[] = {
> 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> };
> define_sfdp_read(w25q01jvq);
> +
> +/*
> + * Integrated Silicon Solution (ISSI)
> + */
> +
> +static const uint8_t sfdp_is25wp256[] = {
> + 0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
> + 0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
> + 0x9d, 0x05, 0x01, 0x03, 0x80, 0x00, 0x00, 0x02,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xe5, 0x20, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x0f,
> + 0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x80, 0xbb,
> + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
> + 0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
> + 0x10, 0xd8, 0x00, 0xff, 0x23, 0x4a, 0xc9, 0x00,
> + 0x82, 0xd8, 0x11, 0xce, 0xcc, 0xcd, 0x68, 0x46,
> + 0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xae, 0xd5, 0x5c,
> + 0x4a, 0x42, 0x2c, 0xff, 0xf0, 0x30, 0xfa, 0xa9,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0x50, 0x19, 0x50, 0x16, 0x9f, 0xf9, 0xc0, 0x64,
> + 0x8f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +};
> +define_sfdp_read(is25wp256);
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 06/25] tests/avocado/machine_aspeed.py: update buildroot tests
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (4 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 05/25] m25p80: Add the is25wp256 SFPD table Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:47 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 07/25] tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot Cédric Le Goater
` (18 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Cédric Le Goater
Use buildroot 2022.11 based images plus some customization :
- Linux version is bumped to 6.0.9 and kernel is built with a custom
config similar to what OpenBMC provides.
- U-Boot is switched to the one provided by OpenBMC for better support.
- defconfigs includes more target tools for dev.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/avocado/machine_aspeed.py | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index 1fc385e1c8..773b1ff3a9 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -123,8 +123,8 @@ def test_arm_ast2500_evb_buildroot(self):
"""
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
- 'images/ast2500-evb/buildroot-2022.05/flash.img')
- image_hash = ('549db6e9d8cdaf4367af21c36385a68bb465779c18b5e37094fc7343decccd3f')
+ 'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
+ image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
@@ -151,8 +151,8 @@ def test_arm_ast2600_evb_buildroot(self):
"""
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
- 'images/ast2600-evb/buildroot-2022.05/flash.img')
- image_hash = ('6cc9e7d128fd4fa1fd01c883af67593cae8072c3239a0b8b6ace857f3538a92d')
+ 'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
+ image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 06/25] tests/avocado/machine_aspeed.py: update buildroot tests
2023-01-19 12:34 ` [PATCH 06/25] tests/avocado/machine_aspeed.py: update buildroot tests Cédric Le Goater
@ 2023-02-01 5:47 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:47 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé
On Thu, 19 Jan 2023 at 12:37, Cédric Le Goater <clg@kaod.org> wrote:
>
> Use buildroot 2022.11 based images plus some customization :
>
> - Linux version is bumped to 6.0.9 and kernel is built with a custom
> config similar to what OpenBMC provides.
> - U-Boot is switched to the one provided by OpenBMC for better support.
> - defconfigs includes more target tools for dev.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> tests/avocado/machine_aspeed.py | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
> index 1fc385e1c8..773b1ff3a9 100644
> --- a/tests/avocado/machine_aspeed.py
> +++ b/tests/avocado/machine_aspeed.py
> @@ -123,8 +123,8 @@ def test_arm_ast2500_evb_buildroot(self):
> """
>
> image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
> - 'images/ast2500-evb/buildroot-2022.05/flash.img')
> - image_hash = ('549db6e9d8cdaf4367af21c36385a68bb465779c18b5e37094fc7343decccd3f')
> + 'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
> + image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
> image_path = self.fetch_asset(image_url, asset_hash=image_hash,
> algorithm='sha256')
>
> @@ -151,8 +151,8 @@ def test_arm_ast2600_evb_buildroot(self):
> """
>
> image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
> - 'images/ast2600-evb/buildroot-2022.05/flash.img')
> - image_hash = ('6cc9e7d128fd4fa1fd01c883af67593cae8072c3239a0b8b6ace857f3538a92d')
> + 'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
> + image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
> image_path = self.fetch_asset(image_url, asset_hash=image_hash,
> algorithm='sha256')
>
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 07/25] tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (5 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 06/25] tests/avocado/machine_aspeed.py: update buildroot tests Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:42 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 08/25] hw/arm/boot: Export write_bootloader for Aspeed machines Cédric Le Goater
` (17 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/avocado/machine_aspeed.py | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index 773b1ff3a9..1cab946727 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -183,7 +183,14 @@ def test_arm_ast2600_evb_buildroot(self):
class AST2x00MachineSDK(QemuSystemTest):
- EXTRA_BOOTARGS = ' quiet'
+ EXTRA_BOOTARGS = (
+ 'quiet '
+ 'systemd.mask=org.openbmc.HostIpmi.service '
+ 'systemd.mask=xyz.openbmc_project.Chassis.Control.Power@0.service '
+ 'systemd.mask=modprobe@fuse.service '
+ 'systemd.mask=rngd.service '
+ 'systemd.mask=obmc-console@ttyS2.service '
+ )
# FIXME: Although these tests boot a whole distro they are still
# slower than comparable machine models. There may be some
@@ -208,7 +215,7 @@ def do_test_arm_aspeed_sdk_start(self, image):
interrupt_interactive_console_until_pattern(
self, 'Hit any key to stop autoboot:', 'ast#')
exec_command_and_wait_for_pattern(
- self, 'setenv bootargs ${bootargs}' + self.EXTRA_BOOTARGS, 'ast#')
+ self, 'setenv bootargs ${bootargs} ' + self.EXTRA_BOOTARGS, 'ast#')
exec_command_and_wait_for_pattern(
self, 'boot', '## Loading kernel from FIT Image')
self.wait_for_console_pattern('Starting kernel ...')
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 07/25] tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
2023-01-19 12:34 ` [PATCH 07/25] tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot Cédric Le Goater
@ 2023-02-01 5:42 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:42 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé,
Andrew Jeffery
On Thu, 19 Jan 2023 at 12:39, Cédric Le Goater <clg@kaod.org> wrote:
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
NIce!
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> tests/avocado/machine_aspeed.py | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
> index 773b1ff3a9..1cab946727 100644
> --- a/tests/avocado/machine_aspeed.py
> +++ b/tests/avocado/machine_aspeed.py
> @@ -183,7 +183,14 @@ def test_arm_ast2600_evb_buildroot(self):
>
> class AST2x00MachineSDK(QemuSystemTest):
>
> - EXTRA_BOOTARGS = ' quiet'
> + EXTRA_BOOTARGS = (
> + 'quiet '
> + 'systemd.mask=org.openbmc.HostIpmi.service '
> + 'systemd.mask=xyz.openbmc_project.Chassis.Control.Power@0.service '
> + 'systemd.mask=modprobe@fuse.service '
> + 'systemd.mask=rngd.service '
> + 'systemd.mask=obmc-console@ttyS2.service '
> + )
>
> # FIXME: Although these tests boot a whole distro they are still
> # slower than comparable machine models. There may be some
> @@ -208,7 +215,7 @@ def do_test_arm_aspeed_sdk_start(self, image):
> interrupt_interactive_console_until_pattern(
> self, 'Hit any key to stop autoboot:', 'ast#')
> exec_command_and_wait_for_pattern(
> - self, 'setenv bootargs ${bootargs}' + self.EXTRA_BOOTARGS, 'ast#')
> + self, 'setenv bootargs ${bootargs} ' + self.EXTRA_BOOTARGS, 'ast#')
> exec_command_and_wait_for_pattern(
> self, 'boot', '## Loading kernel from FIT Image')
> self.wait_for_console_pattern('Starting kernel ...')
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 08/25] hw/arm/boot: Export write_bootloader for Aspeed machines
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (6 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 07/25] tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:45 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 09/25] hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr Cédric Le Goater
` (16 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Cédric Le Goater
AST2600 Aspeed machines have an home made boot loader for secondaries.
To improve support, export the internal ARM boot loader and use it
instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/boot.h | 24 ++++++++++++++++++++++++
hw/arm/aspeed.c | 42 ++++++++++++++++++++++--------------------
hw/arm/boot.c | 34 +++++++---------------------------
3 files changed, 53 insertions(+), 47 deletions(-)
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index f18cc3064f..23edd0d31b 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -183,4 +183,28 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
const struct arm_boot_info *info,
hwaddr mvbar_addr);
+typedef enum {
+ FIXUP_NONE = 0, /* do nothing */
+ FIXUP_TERMINATOR, /* end of insns */
+ FIXUP_BOARDID, /* overwrite with board ID number */
+ FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
+ FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
+ FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
+ FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
+ FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
+ FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
+ FIXUP_BOOTREG, /* overwrite with boot register address */
+ FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
+ FIXUP_MAX,
+} FixupType;
+
+typedef struct ARMInsnFixup {
+ uint32_t insn;
+ FixupType fixup;
+} ARMInsnFixup;
+
+void arm_write_bootloader(const char *name, hwaddr addr,
+ const ARMInsnFixup *insns, uint32_t *fixupcontext,
+ AddressSpace *as);
+
#endif /* HW_ARM_BOOT_H */
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 4919a1fe9e..c373bd2851 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -198,33 +198,35 @@ struct AspeedMachineState {
static void aspeed_write_smpboot(ARMCPU *cpu,
const struct arm_boot_info *info)
{
- static const uint32_t poll_mailbox_ready[] = {
+ AddressSpace *as = arm_boot_address_space(cpu, info);
+ static const ARMInsnFixup poll_mailbox_ready[] = {
/*
* r2 = per-cpu go sign value
* r1 = AST_SMP_MBOX_FIELD_ENTRY
* r0 = AST_SMP_MBOX_FIELD_GOSIGN
*/
- 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
- 0xe21000ff, /* ands r0, r0, #255 */
- 0xe59f201c, /* ldr r2, [pc, #28] */
- 0xe1822000, /* orr r2, r2, r0 */
-
- 0xe59f1018, /* ldr r1, [pc, #24] */
- 0xe59f0018, /* ldr r0, [pc, #24] */
-
- 0xe320f002, /* wfe */
- 0xe5904000, /* ldr r4, [r0] */
- 0xe1520004, /* cmp r2, r4 */
- 0x1afffffb, /* bne <wfe> */
- 0xe591f000, /* ldr pc, [r1] */
- AST_SMP_MBOX_GOSIGN,
- AST_SMP_MBOX_FIELD_ENTRY,
- AST_SMP_MBOX_FIELD_GOSIGN,
+ { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
+ { 0xe21000ff }, /* ands r0, r0, #255 */
+ { 0xe59f201c }, /* ldr r2, [pc, #28] */
+ { 0xe1822000 }, /* orr r2, r2, r0 */
+
+ { 0xe59f1018 }, /* ldr r1, [pc, #24] */
+ { 0xe59f0018 }, /* ldr r0, [pc, #24] */
+
+ { 0xe320f002 }, /* wfe */
+ { 0xe5904000 }, /* ldr r4, [r0] */
+ { 0xe1520004 }, /* cmp r2, r4 */
+ { 0x1afffffb }, /* bne <wfe> */
+ { 0xe591f000 }, /* ldr pc, [r1] */
+ { AST_SMP_MBOX_GOSIGN },
+ { AST_SMP_MBOX_FIELD_ENTRY },
+ { AST_SMP_MBOX_FIELD_GOSIGN },
+ { 0, FIXUP_TERMINATOR }
};
+ uint32_t fixupcontext[FIXUP_MAX] = { 0 };
- rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
- sizeof(poll_mailbox_ready),
- info->smp_loader_start);
+ arm_write_bootloader("aspeed.smpboot", info->smp_loader_start,
+ poll_mailbox_ready, fixupcontext, as);
}
static void aspeed_reset_secondary(ARMCPU *cpu,
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 3d7d11f782..ed6fd7c77f 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -59,26 +59,6 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
return cpu_get_address_space(cs, asidx);
}
-typedef enum {
- FIXUP_NONE = 0, /* do nothing */
- FIXUP_TERMINATOR, /* end of insns */
- FIXUP_BOARDID, /* overwrite with board ID number */
- FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
- FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
- FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
- FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
- FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
- FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
- FIXUP_BOOTREG, /* overwrite with boot register address */
- FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
- FIXUP_MAX,
-} FixupType;
-
-typedef struct ARMInsnFixup {
- uint32_t insn;
- FixupType fixup;
-} ARMInsnFixup;
-
static const ARMInsnFixup bootloader_aarch64[] = {
{ 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
{ 0xaa1f03e1 }, /* mov x1, xzr */
@@ -149,9 +129,9 @@ static const ARMInsnFixup smpboot[] = {
{ 0, FIXUP_TERMINATOR }
};
-static void write_bootloader(const char *name, hwaddr addr,
- const ARMInsnFixup *insns, uint32_t *fixupcontext,
- AddressSpace *as)
+void arm_write_bootloader(const char *name, hwaddr addr,
+ const ARMInsnFixup *insns, uint32_t *fixupcontext,
+ AddressSpace *as)
{
/* Fix up the specified bootloader fragment and write it into
* guest memory using rom_add_blob_fixed(). fixupcontext is
@@ -213,8 +193,8 @@ static void default_write_secondary(ARMCPU *cpu,
fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
}
- write_bootloader("smpboot", info->smp_loader_start,
- smpboot, fixupcontext, as);
+ arm_write_bootloader("smpboot", info->smp_loader_start,
+ smpboot, fixupcontext, as);
}
void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
@@ -1173,8 +1153,8 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
- write_bootloader("bootloader", info->loader_start,
- primary_loader, fixupcontext, as);
+ arm_write_bootloader("bootloader", info->loader_start,
+ primary_loader, fixupcontext, as);
if (info->write_board_setup) {
info->write_board_setup(cpu, info);
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 08/25] hw/arm/boot: Export write_bootloader for Aspeed machines
2023-01-19 12:34 ` [PATCH 08/25] hw/arm/boot: Export write_bootloader for Aspeed machines Cédric Le Goater
@ 2023-02-01 5:45 ` Joel Stanley
2023-02-01 7:58 ` Cédric Le Goater
0 siblings, 1 reply; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:45 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé
On Thu, 19 Jan 2023 at 12:37, Cédric Le Goater <clg@kaod.org> wrote:
>
> AST2600 Aspeed machines have an home made boot loader for secondaries.
> To improve support, export the internal ARM boot loader and use it
> instead.
I didn't quite follow why we're doing this. Is it just a cleanup?
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/arm/boot.h | 24 ++++++++++++++++++++++++
> hw/arm/aspeed.c | 42 ++++++++++++++++++++++--------------------
> hw/arm/boot.c | 34 +++++++---------------------------
> 3 files changed, 53 insertions(+), 47 deletions(-)
>
> diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
> index f18cc3064f..23edd0d31b 100644
> --- a/include/hw/arm/boot.h
> +++ b/include/hw/arm/boot.h
> @@ -183,4 +183,28 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
> const struct arm_boot_info *info,
> hwaddr mvbar_addr);
>
> +typedef enum {
> + FIXUP_NONE = 0, /* do nothing */
> + FIXUP_TERMINATOR, /* end of insns */
> + FIXUP_BOARDID, /* overwrite with board ID number */
> + FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
> + FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
> + FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
> + FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
> + FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
> + FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
> + FIXUP_BOOTREG, /* overwrite with boot register address */
> + FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
> + FIXUP_MAX,
> +} FixupType;
> +
> +typedef struct ARMInsnFixup {
> + uint32_t insn;
> + FixupType fixup;
> +} ARMInsnFixup;
> +
> +void arm_write_bootloader(const char *name, hwaddr addr,
> + const ARMInsnFixup *insns, uint32_t *fixupcontext,
> + AddressSpace *as);
> +
> #endif /* HW_ARM_BOOT_H */
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 4919a1fe9e..c373bd2851 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -198,33 +198,35 @@ struct AspeedMachineState {
> static void aspeed_write_smpboot(ARMCPU *cpu,
> const struct arm_boot_info *info)
> {
> - static const uint32_t poll_mailbox_ready[] = {
> + AddressSpace *as = arm_boot_address_space(cpu, info);
> + static const ARMInsnFixup poll_mailbox_ready[] = {
> /*
> * r2 = per-cpu go sign value
> * r1 = AST_SMP_MBOX_FIELD_ENTRY
> * r0 = AST_SMP_MBOX_FIELD_GOSIGN
> */
> - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
> - 0xe21000ff, /* ands r0, r0, #255 */
> - 0xe59f201c, /* ldr r2, [pc, #28] */
> - 0xe1822000, /* orr r2, r2, r0 */
> -
> - 0xe59f1018, /* ldr r1, [pc, #24] */
> - 0xe59f0018, /* ldr r0, [pc, #24] */
> -
> - 0xe320f002, /* wfe */
> - 0xe5904000, /* ldr r4, [r0] */
> - 0xe1520004, /* cmp r2, r4 */
> - 0x1afffffb, /* bne <wfe> */
> - 0xe591f000, /* ldr pc, [r1] */
> - AST_SMP_MBOX_GOSIGN,
> - AST_SMP_MBOX_FIELD_ENTRY,
> - AST_SMP_MBOX_FIELD_GOSIGN,
> + { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
> + { 0xe21000ff }, /* ands r0, r0, #255 */
> + { 0xe59f201c }, /* ldr r2, [pc, #28] */
> + { 0xe1822000 }, /* orr r2, r2, r0 */
> +
> + { 0xe59f1018 }, /* ldr r1, [pc, #24] */
> + { 0xe59f0018 }, /* ldr r0, [pc, #24] */
> +
> + { 0xe320f002 }, /* wfe */
> + { 0xe5904000 }, /* ldr r4, [r0] */
> + { 0xe1520004 }, /* cmp r2, r4 */
> + { 0x1afffffb }, /* bne <wfe> */
> + { 0xe591f000 }, /* ldr pc, [r1] */
> + { AST_SMP_MBOX_GOSIGN },
> + { AST_SMP_MBOX_FIELD_ENTRY },
> + { AST_SMP_MBOX_FIELD_GOSIGN },
> + { 0, FIXUP_TERMINATOR }
> };
> + uint32_t fixupcontext[FIXUP_MAX] = { 0 };
>
> - rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
> - sizeof(poll_mailbox_ready),
> - info->smp_loader_start);
> + arm_write_bootloader("aspeed.smpboot", info->smp_loader_start,
> + poll_mailbox_ready, fixupcontext, as);
> }
>
> static void aspeed_reset_secondary(ARMCPU *cpu,
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
> index 3d7d11f782..ed6fd7c77f 100644
> --- a/hw/arm/boot.c
> +++ b/hw/arm/boot.c
> @@ -59,26 +59,6 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
> return cpu_get_address_space(cs, asidx);
> }
>
> -typedef enum {
> - FIXUP_NONE = 0, /* do nothing */
> - FIXUP_TERMINATOR, /* end of insns */
> - FIXUP_BOARDID, /* overwrite with board ID number */
> - FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
> - FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
> - FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
> - FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
> - FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
> - FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
> - FIXUP_BOOTREG, /* overwrite with boot register address */
> - FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
> - FIXUP_MAX,
> -} FixupType;
> -
> -typedef struct ARMInsnFixup {
> - uint32_t insn;
> - FixupType fixup;
> -} ARMInsnFixup;
> -
> static const ARMInsnFixup bootloader_aarch64[] = {
> { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
> { 0xaa1f03e1 }, /* mov x1, xzr */
> @@ -149,9 +129,9 @@ static const ARMInsnFixup smpboot[] = {
> { 0, FIXUP_TERMINATOR }
> };
>
> -static void write_bootloader(const char *name, hwaddr addr,
> - const ARMInsnFixup *insns, uint32_t *fixupcontext,
> - AddressSpace *as)
> +void arm_write_bootloader(const char *name, hwaddr addr,
> + const ARMInsnFixup *insns, uint32_t *fixupcontext,
> + AddressSpace *as)
> {
> /* Fix up the specified bootloader fragment and write it into
> * guest memory using rom_add_blob_fixed(). fixupcontext is
> @@ -213,8 +193,8 @@ static void default_write_secondary(ARMCPU *cpu,
> fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
> }
>
> - write_bootloader("smpboot", info->smp_loader_start,
> - smpboot, fixupcontext, as);
> + arm_write_bootloader("smpboot", info->smp_loader_start,
> + smpboot, fixupcontext, as);
> }
>
> void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
> @@ -1173,8 +1153,8 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
> fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
> fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
>
> - write_bootloader("bootloader", info->loader_start,
> - primary_loader, fixupcontext, as);
> + arm_write_bootloader("bootloader", info->loader_start,
> + primary_loader, fixupcontext, as);
>
> if (info->write_board_setup) {
> info->write_board_setup(cpu, info);
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH 08/25] hw/arm/boot: Export write_bootloader for Aspeed machines
2023-02-01 5:45 ` Joel Stanley
@ 2023-02-01 7:58 ` Cédric Le Goater
2023-02-01 12:20 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-02-01 7:58 UTC (permalink / raw)
To: Joel Stanley
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé
On 2/1/23 06:45, Joel Stanley wrote:
> On Thu, 19 Jan 2023 at 12:37, Cédric Le Goater <clg@kaod.org> wrote:
>>
>> AST2600 Aspeed machines have an home made boot loader for secondaries.
>> To improve support, export the internal ARM boot loader and use it
>> instead.
>
> I didn't quite follow why we're doing this. Is it just a cleanup?
It comes from this discussion :
https://lore.kernel.org/qemu-devel/20221222215549.86872-1-philmd@linaro.org/
I will leave Phil handle it. The patch is on the list now.
Thanks,
C.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/arm/boot.h | 24 ++++++++++++++++++++++++
>> hw/arm/aspeed.c | 42 ++++++++++++++++++++++--------------------
>> hw/arm/boot.c | 34 +++++++---------------------------
>> 3 files changed, 53 insertions(+), 47 deletions(-)
>>
>> diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
>> index f18cc3064f..23edd0d31b 100644
>> --- a/include/hw/arm/boot.h
>> +++ b/include/hw/arm/boot.h
>> @@ -183,4 +183,28 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
>> const struct arm_boot_info *info,
>> hwaddr mvbar_addr);
>>
>> +typedef enum {
>> + FIXUP_NONE = 0, /* do nothing */
>> + FIXUP_TERMINATOR, /* end of insns */
>> + FIXUP_BOARDID, /* overwrite with board ID number */
>> + FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
>> + FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
>> + FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
>> + FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
>> + FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
>> + FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
>> + FIXUP_BOOTREG, /* overwrite with boot register address */
>> + FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
>> + FIXUP_MAX,
>> +} FixupType;
>> +
>> +typedef struct ARMInsnFixup {
>> + uint32_t insn;
>> + FixupType fixup;
>> +} ARMInsnFixup;
>> +
>> +void arm_write_bootloader(const char *name, hwaddr addr,
>> + const ARMInsnFixup *insns, uint32_t *fixupcontext,
>> + AddressSpace *as);
>> +
>> #endif /* HW_ARM_BOOT_H */
>> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
>> index 4919a1fe9e..c373bd2851 100644
>> --- a/hw/arm/aspeed.c
>> +++ b/hw/arm/aspeed.c
>> @@ -198,33 +198,35 @@ struct AspeedMachineState {
>> static void aspeed_write_smpboot(ARMCPU *cpu,
>> const struct arm_boot_info *info)
>> {
>> - static const uint32_t poll_mailbox_ready[] = {
>> + AddressSpace *as = arm_boot_address_space(cpu, info);
>> + static const ARMInsnFixup poll_mailbox_ready[] = {
>> /*
>> * r2 = per-cpu go sign value
>> * r1 = AST_SMP_MBOX_FIELD_ENTRY
>> * r0 = AST_SMP_MBOX_FIELD_GOSIGN
>> */
>> - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
>> - 0xe21000ff, /* ands r0, r0, #255 */
>> - 0xe59f201c, /* ldr r2, [pc, #28] */
>> - 0xe1822000, /* orr r2, r2, r0 */
>> -
>> - 0xe59f1018, /* ldr r1, [pc, #24] */
>> - 0xe59f0018, /* ldr r0, [pc, #24] */
>> -
>> - 0xe320f002, /* wfe */
>> - 0xe5904000, /* ldr r4, [r0] */
>> - 0xe1520004, /* cmp r2, r4 */
>> - 0x1afffffb, /* bne <wfe> */
>> - 0xe591f000, /* ldr pc, [r1] */
>> - AST_SMP_MBOX_GOSIGN,
>> - AST_SMP_MBOX_FIELD_ENTRY,
>> - AST_SMP_MBOX_FIELD_GOSIGN,
>> + { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
>> + { 0xe21000ff }, /* ands r0, r0, #255 */
>> + { 0xe59f201c }, /* ldr r2, [pc, #28] */
>> + { 0xe1822000 }, /* orr r2, r2, r0 */
>> +
>> + { 0xe59f1018 }, /* ldr r1, [pc, #24] */
>> + { 0xe59f0018 }, /* ldr r0, [pc, #24] */
>> +
>> + { 0xe320f002 }, /* wfe */
>> + { 0xe5904000 }, /* ldr r4, [r0] */
>> + { 0xe1520004 }, /* cmp r2, r4 */
>> + { 0x1afffffb }, /* bne <wfe> */
>> + { 0xe591f000 }, /* ldr pc, [r1] */
>> + { AST_SMP_MBOX_GOSIGN },
>> + { AST_SMP_MBOX_FIELD_ENTRY },
>> + { AST_SMP_MBOX_FIELD_GOSIGN },
>> + { 0, FIXUP_TERMINATOR }
>> };
>> + uint32_t fixupcontext[FIXUP_MAX] = { 0 };
>>
>> - rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
>> - sizeof(poll_mailbox_ready),
>> - info->smp_loader_start);
>> + arm_write_bootloader("aspeed.smpboot", info->smp_loader_start,
>> + poll_mailbox_ready, fixupcontext, as);
>> }
>>
>> static void aspeed_reset_secondary(ARMCPU *cpu,
>> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
>> index 3d7d11f782..ed6fd7c77f 100644
>> --- a/hw/arm/boot.c
>> +++ b/hw/arm/boot.c
>> @@ -59,26 +59,6 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
>> return cpu_get_address_space(cs, asidx);
>> }
>>
>> -typedef enum {
>> - FIXUP_NONE = 0, /* do nothing */
>> - FIXUP_TERMINATOR, /* end of insns */
>> - FIXUP_BOARDID, /* overwrite with board ID number */
>> - FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
>> - FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
>> - FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
>> - FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
>> - FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
>> - FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
>> - FIXUP_BOOTREG, /* overwrite with boot register address */
>> - FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
>> - FIXUP_MAX,
>> -} FixupType;
>> -
>> -typedef struct ARMInsnFixup {
>> - uint32_t insn;
>> - FixupType fixup;
>> -} ARMInsnFixup;
>> -
>> static const ARMInsnFixup bootloader_aarch64[] = {
>> { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
>> { 0xaa1f03e1 }, /* mov x1, xzr */
>> @@ -149,9 +129,9 @@ static const ARMInsnFixup smpboot[] = {
>> { 0, FIXUP_TERMINATOR }
>> };
>>
>> -static void write_bootloader(const char *name, hwaddr addr,
>> - const ARMInsnFixup *insns, uint32_t *fixupcontext,
>> - AddressSpace *as)
>> +void arm_write_bootloader(const char *name, hwaddr addr,
>> + const ARMInsnFixup *insns, uint32_t *fixupcontext,
>> + AddressSpace *as)
>> {
>> /* Fix up the specified bootloader fragment and write it into
>> * guest memory using rom_add_blob_fixed(). fixupcontext is
>> @@ -213,8 +193,8 @@ static void default_write_secondary(ARMCPU *cpu,
>> fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
>> }
>>
>> - write_bootloader("smpboot", info->smp_loader_start,
>> - smpboot, fixupcontext, as);
>> + arm_write_bootloader("smpboot", info->smp_loader_start,
>> + smpboot, fixupcontext, as);
>> }
>>
>> void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
>> @@ -1173,8 +1153,8 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
>> fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
>> fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
>>
>> - write_bootloader("bootloader", info->loader_start,
>> - primary_loader, fixupcontext, as);
>> + arm_write_bootloader("bootloader", info->loader_start,
>> + primary_loader, fixupcontext, as);
>>
>> if (info->write_board_setup) {
>> info->write_board_setup(cpu, info);
>> --
>> 2.39.0
>>
>>
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH 08/25] hw/arm/boot: Export write_bootloader for Aspeed machines
2023-02-01 7:58 ` Cédric Le Goater
@ 2023-02-01 12:20 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 42+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-01 12:20 UTC (permalink / raw)
To: Cédric Le Goater, Joel Stanley; +Cc: qemu-arm, qemu-devel, Peter Maydell
On 1/2/23 08:58, Cédric Le Goater wrote:
> On 2/1/23 06:45, Joel Stanley wrote:
>> On Thu, 19 Jan 2023 at 12:37, Cédric Le Goater <clg@kaod.org> wrote:
>>>
>>> AST2600 Aspeed machines have an home made boot loader for secondaries.
>>> To improve support, export the internal ARM boot loader and use it
>>> instead.
>>
>> I didn't quite follow why we're doing this. Is it just a cleanup?
>
> It comes from this discussion :
>
>
> https://lore.kernel.org/qemu-devel/20221222215549.86872-1-philmd@linaro.org/
Joel, see:
https://lore.kernel.org/qemu-devel/CAFEAcA9KD8WwPTKVQQUfAZxaqA=ASweZtJ=sAV0Vd8TkpqDBOw@mail.gmail.com/
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 09/25] hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (7 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 08/25] hw/arm/boot: Export write_bootloader for Aspeed machines Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:45 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 10/25] hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards Cédric Le Goater
` (15 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Cédric Le Goater,
Eduardo Habkost, Marcel Apfelbaum, Alex Bennée
These globals were moved to MachineClass by commit 71ae9e94d9 ("pc: Move
option_rom_has_mr/rom_file_has_mr globals to MachineClass"). Finish cleanup.
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/loader.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index 70248e0da7..1384796a4b 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -251,9 +251,6 @@ void pstrcpy_targphys(const char *name,
hwaddr dest, int buf_size,
const char *source);
-extern bool option_rom_has_mr;
-extern bool rom_file_has_mr;
-
ssize_t rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex,
bool option_rom, MemoryRegion *mr, AddressSpace *as);
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 09/25] hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr
2023-01-19 12:34 ` [PATCH 09/25] hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr Cédric Le Goater
@ 2023-02-01 5:45 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:45 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé,
Eduardo Habkost, Marcel Apfelbaum, Alex Bennée
On Thu, 19 Jan 2023 at 12:37, Cédric Le Goater <clg@kaod.org> wrote:
>
> These globals were moved to MachineClass by commit 71ae9e94d9 ("pc: Move
> option_rom_has_mr/rom_file_has_mr globals to MachineClass"). Finish cleanup.
>
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> Cc: Marcel Apfelbaum <marcel@redhat.com>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> include/hw/loader.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/include/hw/loader.h b/include/hw/loader.h
> index 70248e0da7..1384796a4b 100644
> --- a/include/hw/loader.h
> +++ b/include/hw/loader.h
> @@ -251,9 +251,6 @@ void pstrcpy_targphys(const char *name,
> hwaddr dest, int buf_size,
> const char *source);
>
> -extern bool option_rom_has_mr;
> -extern bool rom_file_has_mr;
> -
> ssize_t rom_add_file(const char *file, const char *fw_dir,
> hwaddr addr, int32_t bootindex,
> bool option_rom, MemoryRegion *mr, AddressSpace *as);
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 10/25] hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (8 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 09/25] hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 11/25] hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init Cédric Le Goater
` (14 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater, Joel Stanley
From: Peter Delevoryas <peter@pjd.dev>
This helper is useful in board initialization because lets users initialize and
realize an EEPROM on an I2C bus with a single function call.
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/nvram/eeprom_at24c.h | 23 +++++++++++++++++++++++
hw/arm/aspeed.c | 10 +---------
hw/arm/npcm7xx_boards.c | 20 +++++---------------
hw/nvram/eeprom_at24c.c | 12 ++++++++++++
4 files changed, 41 insertions(+), 24 deletions(-)
create mode 100644 include/hw/nvram/eeprom_at24c.h
diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
new file mode 100644
index 0000000000..196db309d4
--- /dev/null
+++ b/include/hw/nvram/eeprom_at24c.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#ifndef EEPROM_AT24C_H
+#define EEPROM_AT24C_H
+
+#include "hw/i2c/i2c.h"
+
+/*
+ * Create and realize an AT24C EEPROM device on the heap.
+ * @bus: I2C bus to put it on
+ * @address: I2C address of the EEPROM slave when put on a bus
+ * @rom_size: size of the EEPROM
+ *
+ * Create the device state structure, initialize it, put it on the specified
+ * @bus, and drop the reference to it (the device is realized).
+ */
+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
+
+#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c373bd2851..5f78342a7a 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -17,6 +17,7 @@
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/misc/pca9552.h"
+#include "hw/nvram/eeprom_at24c.h"
#include "hw/sensor/tmp105.h"
#include "hw/misc/led.h"
#include "hw/qdev-properties.h"
@@ -441,15 +442,6 @@ static void aspeed_machine_init(MachineState *machine)
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
}
-static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
-{
- I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
- DeviceState *dev = DEVICE(i2c_dev);
-
- qdev_prop_set_uint32(dev, "rom-size", rsize);
- i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
-}
-
static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 6bc6f5d2fe..9b31207a06 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -21,6 +21,7 @@
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/loader.h"
+#include "hw/nvram/eeprom_at24c.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
@@ -140,17 +141,6 @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
}
-static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
- uint32_t rsize)
-{
- I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
- I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
- DeviceState *dev = DEVICE(i2c_dev);
-
- qdev_prop_set_uint32(dev, "rom-size", rsize);
- i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
-}
-
static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
NPCM7xxState *soc, const int *fan_counts)
{
@@ -253,8 +243,8 @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
- at24c_eeprom_init(soc, 9, 0x55, 8192);
- at24c_eeprom_init(soc, 10, 0x55, 8192);
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);
/*
* i2c-11:
@@ -360,7 +350,7 @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
- at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */
i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
TYPE_PCA9548, 0x77);
@@ -371,7 +361,7 @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
- at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */
/* TODO: Add remaining i2c devices. */
}
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index 2d4d8b952f..98857e3626 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -12,6 +12,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/i2c/i2c.h"
+#include "hw/nvram/eeprom_at24c.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "sysemu/block-backend.h"
@@ -128,6 +129,17 @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
return 0;
}
+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
+{
+ I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
+ DeviceState *dev = DEVICE(i2c_dev);
+
+ qdev_prop_set_uint32(dev, "rom-size", rom_size);
+ i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
+
+ return i2c_dev;
+}
+
static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
{
EEPROMState *ee = AT24C_EE(dev);
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 11/25] hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (9 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 10/25] hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 12/25] hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper Cédric Le Goater
` (13 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater, Joel Stanley
From: Peter Delevoryas <peter@pjd.dev>
aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 95 ++++++++++++++++++++++---------------------------
1 file changed, 43 insertions(+), 52 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 5f78342a7a..e6d541ad0f 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -672,15 +672,6 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
eeprom_buf);
}
-static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
-{
- I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
- DeviceState *dev = DEVICE(i2c_dev);
-
- qdev_prop_set_uint32(dev, "rom-size", rsize);
- i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
-}
-
static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
@@ -713,7 +704,7 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
AspeedSoCState *soc = &bmc->soc;
I2CSlave *i2c_mux;
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
create_pca9552(soc, 3, 0x61);
@@ -726,9 +717,9 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
0x4a);
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
"pca9546", 0x70);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
create_pca9552(soc, 4, 0x60);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
@@ -739,8 +730,8 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
create_pca9552(soc, 5, 0x61);
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
"pca9546", 0x70);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
0x48);
@@ -750,10 +741,10 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
0x4b);
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
"pca9546", 0x70);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
create_pca9552(soc, 7, 0x30);
create_pca9552(soc, 7, 0x31);
@@ -766,15 +757,15 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
0x48);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
0x48);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
0x4a);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
create_pca9552(soc, 8, 0x60);
create_pca9552(soc, 8, 0x61);
/* Bus 8: ucd90320@11 */
@@ -783,11 +774,11 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
0x48);
@@ -795,18 +786,18 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
0x49);
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
"pca9546", 0x70);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
create_pca9552(soc, 11, 0x60);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
create_pca9552(soc, 13, 0x60);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
create_pca9552(soc, 14, 0x60);
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
create_pca9552(soc, 15, 0x60);
}
@@ -850,45 +841,45 @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
- aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
- aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
+ at24c_eeprom_init(i2c[19], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[20], 0x50, 2 * KiB);
+ at24c_eeprom_init(i2c[22], 0x52, 2 * KiB);
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
- aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
+ at24c_eeprom_init(i2c[8], 0x51, 64 * KiB);
i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
- aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[50], 0x52, 64 * KiB);
i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
- aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
+ at24c_eeprom_init(i2c[65], 0x53, 64 * KiB);
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
- aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[68], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[69], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[70], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[71], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
+ at24c_eeprom_init(i2c[73], 0x53, 64 * KiB);
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
- aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
- aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
+ at24c_eeprom_init(i2c[76], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[77], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[78], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[79], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[28], 0x50, 2 * KiB);
for (int i = 0; i < 8; i++) {
- aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
+ at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
@@ -959,11 +950,11 @@ static void fby35_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
- aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
- aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
- aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
- aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
- aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
+ at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
+ at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
+ at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
+ at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
+ at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
/*
* TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 12/25] hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (10 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 11/25] hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 13/25] hw/arm/aspeed: Add aspeed_eeprom.c Cédric Le Goater
` (12 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Joel Stanley, Cédric Le Goater
From: Peter Delevoryas <peter@pjd.dev>
Allows users to specify binary data to initialize an EEPROM, allowing users to
emulate data programmed at manufacturing time.
- Added init_rom and init_rom_size attributes to TYPE_AT24C_EE
- Added at24c_eeprom_init_rom helper function to initialize attributes
- If -drive property is provided, it overrides init_rom data
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/nvram/eeprom_at24c.h | 16 ++++++++++++++
hw/nvram/eeprom_at24c.c | 37 ++++++++++++++++++++++++++++-----
2 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
index 196db309d4..acb9857b2a 100644
--- a/include/hw/nvram/eeprom_at24c.h
+++ b/include/hw/nvram/eeprom_at24c.h
@@ -20,4 +20,20 @@
*/
I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
+
+/*
+ * Create and realize an AT24C EEPROM device on the heap with initial data.
+ * @bus: I2C bus to put it on
+ * @address: I2C address of the EEPROM slave when put on a bus
+ * @rom_size: size of the EEPROM
+ * @init_rom: Array of bytes to initialize EEPROM memory with
+ * @init_rom_size: Size of @init_rom, must be less than or equal to @rom_size
+ *
+ * Create the device state structure, initialize it, put it on the specified
+ * @bus, and drop the reference to it (the device is realized). Copies the data
+ * from @init_rom to the beginning of the EEPROM memory buffer.
+ */
+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
+ const uint8_t *init_rom, uint32_t init_rom_size);
+
#endif
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index 98857e3626..f8d751fa27 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -50,6 +50,9 @@ struct EEPROMState {
uint8_t *mem;
BlockBackend *blk;
+
+ const uint8_t *init_rom;
+ uint32_t init_rom_size;
};
static
@@ -131,19 +134,38 @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
{
- I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
- DeviceState *dev = DEVICE(i2c_dev);
+ return at24c_eeprom_init_rom(bus, address, rom_size, NULL, 0);
+}
+
+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
+ const uint8_t *init_rom, uint32_t init_rom_size)
+{
+ EEPROMState *s;
+
+ s = AT24C_EE(qdev_new(TYPE_AT24C_EE));
+
+ qdev_prop_set_uint8(DEVICE(s), "address", address);
+ qdev_prop_set_uint32(DEVICE(s), "rom-size", rom_size);
- qdev_prop_set_uint32(dev, "rom-size", rom_size);
- i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
+ /* TODO: Model init_rom with QOM properties. */
+ s->init_rom = init_rom;
+ s->init_rom_size = init_rom_size;
- return i2c_dev;
+ i2c_slave_realize_and_unref(I2C_SLAVE(s), bus, &error_abort);
+
+ return I2C_SLAVE(s);
}
static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
{
EEPROMState *ee = AT24C_EE(dev);
+ if (ee->init_rom_size > ee->rsize) {
+ error_setg(errp, "%s: init rom is larger than rom: %u > %u",
+ TYPE_AT24C_EE, ee->init_rom_size, ee->rsize);
+ return;
+ }
+
if (ee->blk) {
int64_t len = blk_getlength(ee->blk);
@@ -163,6 +185,7 @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
}
ee->mem = g_malloc0(ee->rsize);
+
}
static
@@ -176,6 +199,10 @@ void at24c_eeprom_reset(DeviceState *state)
memset(ee->mem, 0, ee->rsize);
+ if (ee->init_rom) {
+ memcpy(ee->mem, ee->init_rom, MIN(ee->init_rom_size, ee->rsize));
+ }
+
if (ee->blk) {
int ret = blk_pread(ee->blk, 0, ee->rsize, ee->mem, 0);
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 13/25] hw/arm/aspeed: Add aspeed_eeprom.c
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (11 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 12/25] hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 14/25] hw/nvram/eeprom_at24c: Make reset behavior more like hardware Cédric Le Goater
` (11 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater, Joel Stanley
From: Peter Delevoryas <peter@pjd.dev>
- Create aspeed_eeprom.c and aspeed_eeprom.h
- Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
- Include aspeed_eeprom.h in aspeed.c
- Add fby35_bmc_fruid data
- Use new at24c_eeprom_init_rom helper to initialize BMC FRUID EEPROM with data
from aspeed_eeprom.c
wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
qemu-system-aarch64 -machine fby35-bmc -nographic -mtdblock fby35.mtd
...
user: root
pass: 0penBmc
...
root@bmc-oob:~# fruid-util bb
FRU Information : Baseboard
--------------- : ------------------
Chassis Type : Rack Mount Chassis
Chassis Part Number : N/A
Chassis Serial Number : N/A
Board Mfg Date : Fri Jan 7 10:30:00 2022
Board Mfg : XXXXXX
Board Product : Management Board wBMC
Board Serial : XXXXXXXXXXXXX
Board Part Number : XXXXXXXXXXXXXX
Board FRU ID : 1.0
Board Custom Data 1 : XXXXXXXXX
Board Custom Data 2 : XXXXXXXXXXXXXXXXXX
Product Manufacturer : XXXXXX
Product Name : Yosemite V3.5 EVT2
Product Part Number : XXXXXXXXXXXXXX
Product Version : EVT2
Product Serial : XXXXXXXXXXXXX
Product Asset Tag : XXXXXXX
Product FRU ID : 1.0
Product Custom Data 1 : XXXXXXXXX
Product Custom Data 2 : N/A
root@bmc-oob:~# fruid-util bmc
FRU Information : BMC
--------------- : ------------------
Board Mfg Date : Mon Jan 10 21:42:00 2022
Board Mfg : XXXXXX
Board Product : BMC Storage Module
Board Serial : XXXXXXXXXXXXX
Board Part Number : XXXXXXXXXXXXXX
Board FRU ID : 1.0
Board Custom Data 1 : XXXXXXXXX
Board Custom Data 2 : XXXXXXXXXXXXXXXXXX
Product Manufacturer : XXXXXX
Product Name : Yosemite V3.5 EVT2
Product Part Number : XXXXXXXXXXXXXX
Product Version : EVT2
Product Serial : XXXXXXXXXXXXX
Product Asset Tag : XXXXXXX
Product FRU ID : 1.0
Product Custom Data 1 : XXXXXXXXX
Product Custom Data 2 : Config A
root@bmc-oob:~# fruid-util nic
FRU Information : NIC
--------------- : ------------------
Board Mfg Date : Tue Nov 2 08:51:00 2021
Board Mfg : XXXXXXXX
Board Product : Mellanox ConnectX-6 DX OCP3.0
Board Serial : XXXXXXXXXXXXXXXXXXXXXXXX
Board Part Number : XXXXXXXXXXXXXXXXXXXXX
Board FRU ID : FRU Ver 0.02
Product Manufacturer : XXXXXXXX
Product Name : Mellanox ConnectX-6 DX OCP3.0
Product Part Number : XXXXXXXXXXXXXXXXXXXXX
Product Version : A9
Product Serial : XXXXXXXXXXXXXXXXXXXXXXXX
Product Custom Data 3 : ConnectX-6 DX
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[ clg: Re-introduced len variables for each array ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed_eeprom.h | 19 ++++++++++
hw/arm/aspeed.c | 10 ++++--
hw/arm/aspeed_eeprom.c | 81 ++++++++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
4 files changed, 108 insertions(+), 3 deletions(-)
create mode 100644 hw/arm/aspeed_eeprom.h
create mode 100644 hw/arm/aspeed_eeprom.c
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
new file mode 100644
index 0000000000..1048e244fc
--- /dev/null
+++ b/hw/arm/aspeed_eeprom.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#ifndef ASPEED_EEPROM_H
+#define ASPEED_EEPROM_H
+
+#include "qemu/osdep.h"
+
+extern const uint8_t fby35_nic_fruid[];
+extern const size_t fby35_nic_fruid_len;
+extern const uint8_t fby35_bb_fruid[];
+extern const size_t fby35_bb_fruid_len;
+extern const uint8_t fby35_bmc_fruid[];
+extern const size_t fby35_bmc_fruid_len;
+
+#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index e6d541ad0f..d07fe702d9 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -14,6 +14,7 @@
#include "hw/arm/boot.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
+#include "hw/arm/aspeed_eeprom.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/misc/pca9552.h"
@@ -952,9 +953,12 @@ static void fby35_i2c_init(AspeedMachineState *bmc)
at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
- at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
- at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
- at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
+ at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
+ fby35_nic_fruid_len);
+ at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
+ fby35_bb_fruid_len);
+ at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
+ fby35_bmc_fruid_len);
/*
* TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
new file mode 100644
index 0000000000..ed50e97d52
--- /dev/null
+++ b/hw/arm/aspeed_eeprom.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#include "aspeed_eeprom.h"
+
+const uint8_t fby35_nic_fruid[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
+ 0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
+ 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f, 0x6e,
+ 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20, 0x4f,
+ 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72,
+ 0x20, 0x30, 0x2e, 0x30, 0x32, 0xc0, 0xc0, 0xc0, 0xc1, 0x00, 0x00, 0x2f,
+ 0x01, 0x11, 0x19, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0xdd, 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f,
+ 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20,
+ 0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xd3, 0x41, 0x39, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63,
+ 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xdb, 0xc0, 0x82, 0x30, 0x15, 0x79, 0x7f, 0xa6, 0x00,
+ 0x01, 0x18, 0x0b, 0xff, 0x08, 0x00, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00,
+ 0x00, 0x03, 0x20, 0x01, 0xff, 0xff, 0x04, 0x46, 0x00, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0x01, 0x81, 0x09, 0x15, 0xb3, 0x10, 0x1d, 0x00,
+ 0x24, 0x15, 0xb3, 0x00, 0x02, 0xeb, 0x8a, 0x95, 0x5c,
+};
+const size_t fby35_nic_fruid_len = G_N_ELEMENTS(fby35_nic_fruid);
+
+const uint8_t fby35_bb_fruid[] = {
+ 0x01, 0x00, 0x01, 0x03, 0x10, 0x00, 0x00, 0xeb, 0x01, 0x02, 0x17, 0xc3,
+ 0x4e, 0x2f, 0x41, 0xc3, 0x4e, 0x2f, 0x41, 0xc1, 0x00, 0x00, 0x00, 0x23,
+ 0x01, 0x0d, 0x00, 0xb6, 0xd2, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xd5, 0x4d, 0x61, 0x6e, 0x61, 0x67, 0x65, 0x6d, 0x65, 0x6e, 0x74,
+ 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x77, 0x42, 0x4d, 0x43, 0xcd,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x01, 0x0c, 0x00, 0xc6,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
+ 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x4e, 0x2f,
+ 0x41, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
+};
+const size_t fby35_bb_fruid_len = G_N_ELEMENTS(fby35_bb_fruid);
+
+const uint8_t fby35_bmc_fruid[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
+ 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
+ 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
+ 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
+ 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
+ 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
+ 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
+};
+const size_t fby35_bmc_fruid_len = G_N_ELEMENTS(fby35_bmc_fruid);
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 76d4d650e4..f70e8cfd45 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -53,6 +53,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed.c',
'aspeed_ast2600.c',
'aspeed_ast10x0.c',
+ 'aspeed_eeprom.c',
'fby35.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 14/25] hw/nvram/eeprom_at24c: Make reset behavior more like hardware
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (12 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 13/25] hw/arm/aspeed: Add aspeed_eeprom.c Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 15/25] target/arm: Allow users to set the number of VFP registers Cédric Le Goater
` (10 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Joel Stanley, Cédric Le Goater
From: Peter Delevoryas <peter@pjd.dev>
EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
I would expect the I2C state machine to be reset to default values, but I
wouldn't really expect the memory to change at all.
The current implementation of the at24c EEPROM resets its internal memory on
reset. This matches the specification in docs/devel/reset.rst:
Cold reset is supported by every resettable object. In QEMU, it means we reset
to the initial state corresponding to the start of QEMU; this might differ
from what is a real hardware cold reset. It differs from other resets (like
warm or bus resets) which may keep certain parts untouched.
But differs from my intuition. For example, if someone writes some information
to an EEPROM, then AC power cycles their board, they would expect the EEPROM to
retain that information. It's very useful to be able to test things like this
in QEMU as well, to verify software instrumentation like determining the cause
of a reboot.
Fixes: 5d8424dbd3e8 ("nvram: add AT24Cx i2c eeprom")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/nvram/eeprom_at24c.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index f8d751fa27..5074776bff 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -185,18 +185,6 @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
}
ee->mem = g_malloc0(ee->rsize);
-
-}
-
-static
-void at24c_eeprom_reset(DeviceState *state)
-{
- EEPROMState *ee = AT24C_EE(state);
-
- ee->changed = false;
- ee->cur = 0;
- ee->haveaddr = 0;
-
memset(ee->mem, 0, ee->rsize);
if (ee->init_rom) {
@@ -214,6 +202,16 @@ void at24c_eeprom_reset(DeviceState *state)
}
}
+static
+void at24c_eeprom_reset(DeviceState *state)
+{
+ EEPROMState *ee = AT24C_EE(state);
+
+ ee->changed = false;
+ ee->cur = 0;
+ ee->haveaddr = 0;
+}
+
static Property at24c_eeprom_props[] = {
DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0),
DEFINE_PROP_BOOL("writable", EEPROMState, writable, true),
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 15/25] target/arm: Allow users to set the number of VFP registers
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (13 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 14/25] hw/nvram/eeprom_at24c: Make reset behavior more like hardware Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-20 8:40 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 16/25] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize' Cédric Le Goater
` (9 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Cédric Le Goater
Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
have 16 64-bit FPU registers and not 32 registers. Let users set the
number of VFP registers with a CPU property.
The primary use case of this property is for the Cortex A7 of the
Aspeed AST2600 SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/arm/cpu.h | 2 ++
hw/arm/aspeed_ast2600.c | 2 ++
target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++
3 files changed, 35 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bf2bce046d..5f2fefef4e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -901,6 +901,8 @@ struct ArchCPU {
bool has_pmu;
/* CPU has VFP */
bool has_vfp;
+ /* CPU has 32 VFP registers */
+ bool has_vfp_d32;
/* CPU has Neon */
bool has_neon;
/* CPU has M-profile DSP extension */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index cd75465c2b..37f43b4165 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -309,6 +309,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
&error_abort);
object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
&error_abort);
+ object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
+ &error_abort);
object_property_set_link(OBJECT(&s->cpu[i]), "memory",
OBJECT(s->memory), &error_abort);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5f63316dbf..ad90de75fb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1269,6 +1269,9 @@ static Property arm_cpu_cfgend_property =
static Property arm_cpu_has_vfp_property =
DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
+static Property arm_cpu_has_vfp_d32_property =
+ DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
+
static Property arm_cpu_has_neon_property =
DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
@@ -1400,6 +1403,14 @@ void arm_cpu_post_init(Object *obj)
}
}
+ if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
+ cpu->has_vfp_d32 = true;
+ if (!kvm_enabled()) {
+ qdev_property_add_static(DEVICE(obj),
+ &arm_cpu_has_vfp_d32_property);
+ }
+ }
+
if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
cpu->has_neon = true;
if (!kvm_enabled()) {
@@ -1661,6 +1672,26 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
+ if (!cpu->has_vfp_d32 &&
+ arm_feature(env, ARM_FEATURE_V8) &&
+ !arm_feature(env, ARM_FEATURE_M)) {
+ error_setg(errp, "ARMv8A CPUs must have VFP32");
+ return;
+ }
+
+ if (cpu->has_vfp_d32 != cpu->has_neon) {
+ error_setg(errp, "ARM CPUs must have both VFP32 and Neon or neither");
+ return;
+ }
+
+ if (!cpu->has_vfp_d32) {
+ uint32_t u;
+
+ u = cpu->isar.mvfr0;
+ u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
+ cpu->isar.mvfr0 = u;
+ }
+
if (!cpu->has_vfp) {
uint64_t t;
uint32_t u;
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 15/25] target/arm: Allow users to set the number of VFP registers
2023-01-19 12:34 ` [PATCH 15/25] target/arm: Allow users to set the number of VFP registers Cédric Le Goater
@ 2023-01-20 8:40 ` Cédric Le Goater
2023-01-20 17:25 ` Peter Maydell
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-20 8:40 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé
On 1/19/23 13:34, Cédric Le Goater wrote:
> Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
> have 16 64-bit FPU registers and not 32 registers. Let users set the
> number of VFP registers with a CPU property.
>
> The primary use case of this property is for the Cortex A7 of the
> Aspeed AST2600 SoC.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/arm/cpu.h | 2 ++
> hw/arm/aspeed_ast2600.c | 2 ++
> target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++
> 3 files changed, 35 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index bf2bce046d..5f2fefef4e 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -901,6 +901,8 @@ struct ArchCPU {
> bool has_pmu;
> /* CPU has VFP */
> bool has_vfp;
> + /* CPU has 32 VFP registers */
> + bool has_vfp_d32;
> /* CPU has Neon */
> bool has_neon;
> /* CPU has M-profile DSP extension */
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index cd75465c2b..37f43b4165 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -309,6 +309,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> &error_abort);
> object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
> &error_abort);
> + object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
> + &error_abort);
> object_property_set_link(OBJECT(&s->cpu[i]), "memory",
> OBJECT(s->memory), &error_abort);
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 5f63316dbf..ad90de75fb 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1269,6 +1269,9 @@ static Property arm_cpu_cfgend_property =
> static Property arm_cpu_has_vfp_property =
> DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
>
> +static Property arm_cpu_has_vfp_d32_property =
> + DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
> +
> static Property arm_cpu_has_neon_property =
> DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
>
> @@ -1400,6 +1403,14 @@ void arm_cpu_post_init(Object *obj)
> }
> }
>
> + if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
> + cpu->has_vfp_d32 = true;
> + if (!kvm_enabled()) {
> + qdev_property_add_static(DEVICE(obj),
> + &arm_cpu_has_vfp_d32_property);
> + }
> + }
> +
> if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
> cpu->has_neon = true;
> if (!kvm_enabled()) {
> @@ -1661,6 +1672,26 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> return;
> }
>
> + if (!cpu->has_vfp_d32 &&
> + arm_feature(env, ARM_FEATURE_V8) &&
> + !arm_feature(env, ARM_FEATURE_M)) {
> + error_setg(errp, "ARMv8A CPUs must have VFP32");
> + return;
> + }
The specs say that the permitted values of the SIMDReg bits [3:0]
in Armv8-A are 0b0000 and 0b0010. In Armv8-M, the possible values
of the field are b0001. All other values are reserved.
This should be better :
if (arm_feature(env, ARM_FEATURE_V8)) {
if (arm_feature(env, ARM_FEATURE_M)) {
if (cpu->has_vfp_d32) {
error_setg(errp, "ARMv8-M CPUs do not support VFP-D32");
return;
}
} else if (!cpu->has_vfp_d32) {
error_setg(errp, "ARMv8-A CPUs must have VFP-D32");
return;
}
}
?
Thanks,
C.
> + if (cpu->has_vfp_d32 != cpu->has_neon) {
> + error_setg(errp, "ARM CPUs must have both VFP32 and Neon or neither");
> + return;
> + }
> +
> + if (!cpu->has_vfp_d32) {
> + uint32_t u;
> +
> + u = cpu->isar.mvfr0;
> + u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
> + cpu->isar.mvfr0 = u;
> + }
> +
> if (!cpu->has_vfp) {
> uint64_t t;
> uint32_t u;
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH 15/25] target/arm: Allow users to set the number of VFP registers
2023-01-20 8:40 ` Cédric Le Goater
@ 2023-01-20 17:25 ` Peter Maydell
0 siblings, 0 replies; 42+ messages in thread
From: Peter Maydell @ 2023-01-20 17:25 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On Fri, 20 Jan 2023 at 08:40, Cédric Le Goater <clg@kaod.org> wrote:
>
> On 1/19/23 13:34, Cédric Le Goater wrote:
> > Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
> > have 16 64-bit FPU registers and not 32 registers. Let users set the
> > number of VFP registers with a CPU property.
> >
> > The primary use case of this property is for the Cortex A7 of the
> > Aspeed AST2600 SoC.
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
> > target/arm/cpu.h | 2 ++
> > hw/arm/aspeed_ast2600.c | 2 ++
> > target/arm/cpu.c | 31 +++++++++++++++++++++++++++++++
> > 3 files changed, 35 insertions(+)
> >
> > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > index bf2bce046d..5f2fefef4e 100644
> > --- a/target/arm/cpu.h
> > +++ b/target/arm/cpu.h
> > @@ -901,6 +901,8 @@ struct ArchCPU {
> > bool has_pmu;
> > /* CPU has VFP */
> > bool has_vfp;
> > + /* CPU has 32 VFP registers */
> > + bool has_vfp_d32;
> > /* CPU has Neon */
> > bool has_neon;
> > /* CPU has M-profile DSP extension */
> > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> > index cd75465c2b..37f43b4165 100644
> > --- a/hw/arm/aspeed_ast2600.c
> > +++ b/hw/arm/aspeed_ast2600.c
> > @@ -309,6 +309,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> > &error_abort);
> > object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
> > &error_abort);
> > + object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
> > + &error_abort);
> > object_property_set_link(OBJECT(&s->cpu[i]), "memory",
> > OBJECT(s->memory), &error_abort);
> >
> > diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> > index 5f63316dbf..ad90de75fb 100644
> > --- a/target/arm/cpu.c
> > +++ b/target/arm/cpu.c
> > @@ -1269,6 +1269,9 @@ static Property arm_cpu_cfgend_property =
> > static Property arm_cpu_has_vfp_property =
> > DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
> >
> > +static Property arm_cpu_has_vfp_d32_property =
> > + DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
> > +
> > static Property arm_cpu_has_neon_property =
> > DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
> >
> > @@ -1400,6 +1403,14 @@ void arm_cpu_post_init(Object *obj)
> > }
> > }
> >
> > + if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
> > + cpu->has_vfp_d32 = true;
> > + if (!kvm_enabled()) {
> > + qdev_property_add_static(DEVICE(obj),
> > + &arm_cpu_has_vfp_d32_property);
> > + }
> > + }
> > +
> > if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
> > cpu->has_neon = true;
> > if (!kvm_enabled()) {
> > @@ -1661,6 +1672,26 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> > return;
> > }
> >
> > + if (!cpu->has_vfp_d32 &&
> > + arm_feature(env, ARM_FEATURE_V8) &&
> > + !arm_feature(env, ARM_FEATURE_M)) {
> > + error_setg(errp, "ARMv8A CPUs must have VFP32");
I wonder if we should instead not create the property for v8A CPUs?
That way there's no way for has_vfp_d32 to get set to false.
But checking after the fact is fine too. (One day we might move away
from the current setup where properties get set up per-object for
Arm CPUs and towards a "the class of the object determines the
properties it has" setup; the way we do it today is a bit odd for
historical reasons.)
> > + return;
> > + }
>
> The specs say that the permitted values of the SIMDReg bits [3:0]
> in Armv8-A are 0b0000 and 0b0010. In Armv8-M, the possible values
> of the field are b0001. All other values are reserved.
>
> This should be better :
>
> if (arm_feature(env, ARM_FEATURE_V8)) {
> if (arm_feature(env, ARM_FEATURE_M)) {
> if (cpu->has_vfp_d32) {
This is unreachable code, because we only set has_vfp_d32 to
true and set up the property if the CPU has the aa32_simd_r32
feature; and v8M CPUs will never have that feature, so
has_vfp_d32 must be false for them here.
(Put another way, we set up the property so we can only
"downgrade" from 32 to 16 dregs, so there is no need to
check whether a CPU that can't have 32 dregs still doesn't have
32 dregs.)
> error_setg(errp, "ARMv8-M CPUs do not support VFP-D32");
> return;
> }
> } else if (!cpu->has_vfp_d32) {
> error_setg(errp, "ARMv8-A CPUs must have VFP-D32");
> return;
> }
> }
>
> ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 16/25] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (14 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 15/25] target/arm: Allow users to set the number of VFP registers Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 17/25] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers Cédric Le Goater
` (8 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Avoid confusing two different things:
- the WDT I/O region size ('iosize')
- at which offset the SoC map the WDT ('offset')
While it is often the same, we can map smaller region sizes
at larger offsets.
Here we are interested in the I/O region size, so rename as
'iosize'.
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[ clg: Introduced temporary wdt_offset variable ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/watchdog/wdt_aspeed.h | 2 +-
hw/arm/aspeed_ast10x0.c | 4 ++--
hw/arm/aspeed_ast2600.c | 4 ++--
hw/arm/aspeed_soc.c | 4 ++--
hw/watchdog/wdt_aspeed.c | 8 ++++----
5 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index dfa5dfa424..db91ee6b51 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -40,7 +40,7 @@ struct AspeedWDTState {
struct AspeedWDTClass {
SysBusDeviceClass parent_class;
- uint32_t offset;
+ uint32_t iosize;
uint32_t ext_pulse_width_mask;
uint32_t reset_ctrl_reg;
void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 4d0b9b115f..b483735dc2 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -318,14 +318,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
/* Watch dog */
for (i = 0; i < sc->wdts_num; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
- sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* GPIO */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 37f43b4165..75add765c6 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -467,14 +467,14 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* Watch dog */
for (i = 0; i < sc->wdts_num; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
- sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* RAM */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index b05b9dd416..e884d6badc 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -386,14 +386,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* Watch dog */
for (i = 0; i < sc->wdts_num; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
- sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* RAM */
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index d753693a2e..958725a1b5 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -309,7 +309,7 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
dc->desc = "ASPEED 2400 Watchdog Controller";
- awc->offset = 0x20;
+ awc->iosize = 0x20;
awc->ext_pulse_width_mask = 0xff;
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
awc->wdt_reload = aspeed_wdt_reload;
@@ -346,7 +346,7 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
dc->desc = "ASPEED 2500 Watchdog Controller";
- awc->offset = 0x20;
+ awc->iosize = 0x20;
awc->ext_pulse_width_mask = 0xfffff;
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
@@ -369,7 +369,7 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
dc->desc = "ASPEED 2600 Watchdog Controller";
- awc->offset = 0x40;
+ awc->iosize = 0x40;
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
@@ -392,7 +392,7 @@ static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
dc->desc = "ASPEED 1030 Watchdog Controller";
- awc->offset = 0x80;
+ awc->iosize = 0x80;
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 17/25] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (15 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 16/25] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize' Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 18/25] hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level Cédric Le Goater
` (7 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When booting the Zephyr demo in [1] we get:
aspeed.io: unimplemented device write (size 4, offset 0x185128, value 0x030f1ff1) <--
aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 0x03fffff1)
This corresponds to this Zephyr code [2]:
static int aspeed_wdt_init(const struct device *dev)
{
const struct aspeed_wdt_config *config = dev->config;
struct aspeed_wdt_data *const data = dev->data;
uint32_t reg_val;
/* disable WDT by default */
reg_val = sys_read32(config->ctrl_base + WDT_CTRL_REG);
reg_val &= ~WDT_CTRL_ENABLE;
sys_write32(reg_val, config->ctrl_base + WDT_CTRL_REG);
sys_write32(data->rst_mask1,
config->ctrl_base + WDT_SW_RESET_MASK1_REG); <------
sys_write32(data->rst_mask2,
config->ctrl_base + WDT_SW_RESET_MASK2_REG);
return 0;
}
The register definitions are [3]:
#define WDT_RELOAD_VAL_REG 0x0004
#define WDT_RESTART_REG 0x0008
#define WDT_CTRL_REG 0x000C
#define WDT_TIMEOUT_STATUS_REG 0x0010
#define WDT_TIMEOUT_STATUS_CLR_REG 0x0014
#define WDT_RESET_MASK1_REG 0x001C
#define WDT_RESET_MASK2_REG 0x0020
#define WDT_SW_RESET_MASK1_REG 0x0028 <------
#define WDT_SW_RESET_MASK2_REG 0x002C
#define WDT_SW_RESET_CTRL_REG 0x0024
Currently QEMU only cover a MMIO region of size 0x20:
#define ASPEED_WDT_REGS_MAX (0x20 / 4)
Change to map the whole 'iosize' which might be bigger, covering
the other registers. The MemoryRegionOps read/write handlers will
report the accesses as out-of-bounds guest-errors, but the next
commit will report them as unimplemented.
[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
[2] https://github.com/AspeedTech-BMC/zephyr/commit/2e99f10ac27b
[3] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/watchdog/wdt_aspeed.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 958725a1b5..eefca31ae4 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -260,6 +260,7 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedWDTState *s = ASPEED_WDT(dev);
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
assert(s->scu);
@@ -271,7 +272,7 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
s->pclk_freq = PCLK_HZ;
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
- TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
+ TYPE_ASPEED_WDT, awc->iosize);
sysbus_init_mmio(sbd, &s->iomem);
}
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 18/25] hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (16 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 17/25] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 19/25] hw/misc/aspeed_hace: Do not crash if address_space_map() failed Cédric Le Goater
` (6 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Add more Aspeed watchdog registers from [*].
Since guests can righteously access them, log the access at
'unimplemented' level instead of 'guest-errors'.
[*] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/watchdog/wdt_aspeed.h | 2 +-
hw/watchdog/wdt_aspeed.c | 13 +++++++++++++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index db91ee6b51..e90ef86651 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -21,7 +21,7 @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
#define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
-#define ASPEED_WDT_REGS_MAX (0x20 / 4)
+#define ASPEED_WDT_REGS_MAX (0x30 / 4)
struct AspeedWDTState {
/*< private >*/
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index eefca31ae4..d267aa185c 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -42,6 +42,11 @@
#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
#define WDT_RESET_MASK1 (0x1c / 4)
+#define WDT_RESET_MASK2 (0x20 / 4)
+
+#define WDT_SW_RESET_CTRL (0x24 / 4)
+#define WDT_SW_RESET_MASK1 (0x28 / 4)
+#define WDT_SW_RESET_MASK2 (0x2c / 4)
#define WDT_TIMEOUT_STATUS (0x10 / 4)
#define WDT_TIMEOUT_CLEAR (0x14 / 4)
@@ -83,6 +88,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
return s->regs[WDT_RESET_MASK1];
case WDT_TIMEOUT_STATUS:
case WDT_TIMEOUT_CLEAR:
+ case WDT_RESET_MASK2:
+ case WDT_SW_RESET_CTRL:
+ case WDT_SW_RESET_MASK1:
+ case WDT_SW_RESET_MASK2:
qemu_log_mask(LOG_UNIMP,
"%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -190,6 +199,10 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
case WDT_TIMEOUT_STATUS:
case WDT_TIMEOUT_CLEAR:
+ case WDT_RESET_MASK2:
+ case WDT_SW_RESET_CTRL:
+ case WDT_SW_RESET_MASK1:
+ case WDT_SW_RESET_MASK2:
qemu_log_mask(LOG_UNIMP,
"%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 19/25] hw/misc/aspeed_hace: Do not crash if address_space_map() failed
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (17 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 18/25] hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 20/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals Cédric Le Goater
` (5 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
address_space_map() can fail:
uart:~$ hash test
sha256_test
tv[0]:
Segmentation fault: 11
Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault.
gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
at ../hw/misc/aspeed_hace.c:171
171 if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) {
(gdb) bt
#0 gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
at ../hw/misc/aspeed_hace.c:171
#1 do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true)
at ../hw/misc/aspeed_hace.c:224
#2 0x00005555559bdbb8 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262488, size=<optimized out>)
at ../hw/misc/aspeed_hace.c:358
This change doesn't fix much, but at least the guest
can't crash QEMU anymore. Instead it is still usable:
uart:~$ hash test
sha256_test
tv[0]:hash_final error
sha384_test
tv[0]:hash_final error
sha512_test
tv[0]:hash_final error
[00:00:06.278,000] <err> hace_global: HACE poll timeout
[00:00:09.324,000] <err> hace_global: HACE poll timeout
[00:00:12.261,000] <err> hace_global: HACE poll timeout
uart:~$
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/aspeed_hace.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index ac21be306c..12a761f1f5 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -193,6 +193,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
size_t digest_len = 0;
int niov = 0;
int i;
+ void *haddr;
if (sg_mode) {
uint32_t len = 0;
@@ -217,9 +218,13 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
addr &= SG_LIST_ADDR_MASK;
plen = len & SG_LIST_LEN_MASK;
- iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false,
- MEMTXATTRS_UNSPECIFIED);
-
+ haddr = address_space_map(&s->dram_as, addr, &plen, false,
+ MEMTXATTRS_UNSPECIFIED);
+ if (haddr == NULL) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
+ return;
+ }
+ iov[i].iov_base = haddr;
if (acc_mode) {
niov = gen_acc_mode_iov(s, iov, i, &plen);
@@ -230,10 +235,14 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
} else {
hwaddr len = s->regs[R_HASH_SRC_LEN];
+ haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
+ &len, false, MEMTXATTRS_UNSPECIFIED);
+ if (haddr == NULL) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
+ return;
+ }
+ iov[0].iov_base = haddr;
iov[0].iov_len = len;
- iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
- &len, false,
- MEMTXATTRS_UNSPECIFIED);
i = 1;
if (s->iov_count) {
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 20/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (18 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 19/25] hw/misc/aspeed_hace: Do not crash if address_space_map() failed Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-02-01 5:54 ` Joel Stanley
2023-01-19 12:34 ` [PATCH 21/25] hw/arm/aspeed_ast10x0: Map I3C peripheral Cédric Le Goater
` (4 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Based on booting Zephyr demo from [1] running QEMU with
'-d unimp' and checking missing devices in [2].
[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
[2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/aspeed_soc.h | 11 +++++++++++
hw/arm/aspeed_ast10x0.c | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 8389200b2d..9a5e3c0bac 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -44,6 +44,7 @@
#define ASPEED_CPUS_NUM 2
#define ASPEED_MACS_NUM 4
#define ASPEED_UARTS_NUM 13
+#define ASPEED_JTAG_NUM 2
struct AspeedSoCState {
/*< private >*/
@@ -87,6 +88,11 @@ struct AspeedSoCState {
UnimplementedDeviceState video;
UnimplementedDeviceState emmc_boot_controller;
UnimplementedDeviceState dpmcu;
+ UnimplementedDeviceState pwm;
+ UnimplementedDeviceState espi;
+ UnimplementedDeviceState udc;
+ UnimplementedDeviceState sgpiom;
+ UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
};
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -174,6 +180,11 @@ enum {
ASPEED_DEV_DPMCU,
ASPEED_DEV_DP,
ASPEED_DEV_I3C,
+ ASPEED_DEV_ESPI,
+ ASPEED_DEV_UDC,
+ ASPEED_DEV_SGPIOM,
+ ASPEED_DEV_JTAG0,
+ ASPEED_DEV_JTAG1,
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index b483735dc2..b970a5ea58 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -27,10 +27,15 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_FMC] = 0x7E620000,
[ASPEED_DEV_SPI1] = 0x7E630000,
[ASPEED_DEV_SPI2] = 0x7E640000,
+ [ASPEED_DEV_UDC] = 0x7E6A2000,
[ASPEED_DEV_SCU] = 0x7E6E2000,
+ [ASPEED_DEV_JTAG0] = 0x7E6E4000,
+ [ASPEED_DEV_JTAG1] = 0x7E6E4100,
[ASPEED_DEV_ADC] = 0x7E6E9000,
+ [ASPEED_DEV_ESPI] = 0x7E6EE000,
[ASPEED_DEV_SBC] = 0x7E6F2000,
[ASPEED_DEV_GPIO] = 0x7E780000,
+ [ASPEED_DEV_SGPIOM] = 0x7E780500,
[ASPEED_DEV_TIMER1] = 0x7E782000,
[ASPEED_DEV_UART1] = 0x7E783000,
[ASPEED_DEV_UART2] = 0x7E78D000,
@@ -78,12 +83,17 @@ static const int aspeed_soc_ast1030_irqmap[] = {
[ASPEED_DEV_LPC] = 35,
[ASPEED_DEV_PECI] = 38,
[ASPEED_DEV_FMC] = 39,
+ [ASPEED_DEV_ESPI] = 42,
[ASPEED_DEV_PWM] = 44,
[ASPEED_DEV_ADC] = 46,
[ASPEED_DEV_SPI1] = 65,
[ASPEED_DEV_SPI2] = 66,
[ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
+ [ASPEED_DEV_UDC] = 9,
+ [ASPEED_DEV_SGPIOM] = 51,
+ [ASPEED_DEV_JTAG0] = 27,
+ [ASPEED_DEV_JTAG1] = 53,
};
static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
@@ -154,6 +164,15 @@ static void aspeed_soc_ast1030_init(Object *obj)
object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "sgpiom", &s->sgpiom,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "jtag[0]", &s->jtag[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "jtag[1]", &s->jtag[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
}
static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
@@ -336,6 +355,22 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
+ sc->memmap[ASPEED_DEV_PWM], 0x100);
+
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
+ sc->memmap[ASPEED_DEV_ESPI], 0x800);
+
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
+ sc->memmap[ASPEED_DEV_UDC], 0x1000);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
+ sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
+
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
+ sc->memmap[ASPEED_DEV_JTAG0], 0x20);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
+ sc->memmap[ASPEED_DEV_JTAG1], 0x20);
}
static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 20/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
2023-01-19 12:34 ` [PATCH 20/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals Cédric Le Goater
@ 2023-02-01 5:54 ` Joel Stanley
0 siblings, 0 replies; 42+ messages in thread
From: Joel Stanley @ 2023-02-01 5:54 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-arm, qemu-devel, Peter Maydell, Philippe Mathieu-Daudé,
Peter Delevoryas
On Thu, 19 Jan 2023 at 12:36, Cédric Le Goater <clg@kaod.org> wrote:
>
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> Based on booting Zephyr demo from [1] running QEMU with
> '-d unimp' and checking missing devices in [2].
>
> [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
> [2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Peter Delevoryas <peter@pjd.dev>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> include/hw/arm/aspeed_soc.h | 11 +++++++++++
> hw/arm/aspeed_ast10x0.c | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 8389200b2d..9a5e3c0bac 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -44,6 +44,7 @@
> #define ASPEED_CPUS_NUM 2
> #define ASPEED_MACS_NUM 4
> #define ASPEED_UARTS_NUM 13
> +#define ASPEED_JTAG_NUM 2
>
> struct AspeedSoCState {
> /*< private >*/
> @@ -87,6 +88,11 @@ struct AspeedSoCState {
> UnimplementedDeviceState video;
> UnimplementedDeviceState emmc_boot_controller;
> UnimplementedDeviceState dpmcu;
> + UnimplementedDeviceState pwm;
> + UnimplementedDeviceState espi;
> + UnimplementedDeviceState udc;
> + UnimplementedDeviceState sgpiom;
> + UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> };
>
> #define TYPE_ASPEED_SOC "aspeed-soc"
> @@ -174,6 +180,11 @@ enum {
> ASPEED_DEV_DPMCU,
> ASPEED_DEV_DP,
> ASPEED_DEV_I3C,
> + ASPEED_DEV_ESPI,
> + ASPEED_DEV_UDC,
> + ASPEED_DEV_SGPIOM,
> + ASPEED_DEV_JTAG0,
> + ASPEED_DEV_JTAG1,
> };
>
> qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index b483735dc2..b970a5ea58 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -27,10 +27,15 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
> [ASPEED_DEV_FMC] = 0x7E620000,
> [ASPEED_DEV_SPI1] = 0x7E630000,
> [ASPEED_DEV_SPI2] = 0x7E640000,
> + [ASPEED_DEV_UDC] = 0x7E6A2000,
> [ASPEED_DEV_SCU] = 0x7E6E2000,
> + [ASPEED_DEV_JTAG0] = 0x7E6E4000,
> + [ASPEED_DEV_JTAG1] = 0x7E6E4100,
> [ASPEED_DEV_ADC] = 0x7E6E9000,
> + [ASPEED_DEV_ESPI] = 0x7E6EE000,
> [ASPEED_DEV_SBC] = 0x7E6F2000,
> [ASPEED_DEV_GPIO] = 0x7E780000,
> + [ASPEED_DEV_SGPIOM] = 0x7E780500,
> [ASPEED_DEV_TIMER1] = 0x7E782000,
> [ASPEED_DEV_UART1] = 0x7E783000,
> [ASPEED_DEV_UART2] = 0x7E78D000,
> @@ -78,12 +83,17 @@ static const int aspeed_soc_ast1030_irqmap[] = {
> [ASPEED_DEV_LPC] = 35,
> [ASPEED_DEV_PECI] = 38,
> [ASPEED_DEV_FMC] = 39,
> + [ASPEED_DEV_ESPI] = 42,
> [ASPEED_DEV_PWM] = 44,
> [ASPEED_DEV_ADC] = 46,
> [ASPEED_DEV_SPI1] = 65,
> [ASPEED_DEV_SPI2] = 66,
> [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
> [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
> + [ASPEED_DEV_UDC] = 9,
> + [ASPEED_DEV_SGPIOM] = 51,
> + [ASPEED_DEV_JTAG0] = 27,
> + [ASPEED_DEV_JTAG1] = 53,
nit: The array is kind of sorted by irq number, these could probably go above?
> };
>
> static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
> @@ -154,6 +164,15 @@ static void aspeed_soc_ast1030_init(Object *obj)
> object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
> TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "sgpiom", &s->sgpiom,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "jtag[0]", &s->jtag[0],
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "jtag[1]", &s->jtag[1],
> + TYPE_UNIMPLEMENTED_DEVICE);
> }
>
> static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> @@ -336,6 +355,22 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> sc->memmap[ASPEED_DEV_GPIO]);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
> +
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
> + sc->memmap[ASPEED_DEV_PWM], 0x100);
> +
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
> + sc->memmap[ASPEED_DEV_ESPI], 0x800);
> +
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
> + sc->memmap[ASPEED_DEV_UDC], 0x1000);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
> + sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
> +
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
> + sc->memmap[ASPEED_DEV_JTAG0], 0x20);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
> + sc->memmap[ASPEED_DEV_JTAG1], 0x20);
> }
>
> static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 21/25] hw/arm/aspeed_ast10x0: Map I3C peripheral
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (19 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 20/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 22/25] hw/arm/aspeed_ast10x0: Map the secure SRAM Cédric Le Goater
` (3 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Since I don't have access to the datasheet, the relevant
values were found in:
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index b970a5ea58..1a06269cb1 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -53,6 +53,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_WDT] = 0x7E785000,
[ASPEED_DEV_LPC] = 0x7E789000,
[ASPEED_DEV_PECI] = 0x7E78B000,
+ [ASPEED_DEV_I3C] = 0x7E7A0000,
[ASPEED_DEV_I2C] = 0x7E7B0000,
};
@@ -88,6 +89,7 @@ static const int aspeed_soc_ast1030_irqmap[] = {
[ASPEED_DEV_ADC] = 46,
[ASPEED_DEV_SPI1] = 65,
[ASPEED_DEV_SPI2] = 66,
+ [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */
[ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
[ASPEED_DEV_UDC] = 9,
@@ -129,6 +131,8 @@ static void aspeed_soc_ast1030_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
object_initialize_child(obj, "i2c", &s->i2c, typename);
+ object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
+
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
@@ -239,6 +243,18 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
}
+ /* I3C */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
+ for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+ sc->irqmap[ASPEED_DEV_I3C] + i);
+ /* The AST1030 I3C controller has one IRQ per bus. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
+ }
+
/* PECI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
return;
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 22/25] hw/arm/aspeed_ast10x0: Map the secure SRAM
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (20 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 21/25] hw/arm/aspeed_ast10x0: Map I3C peripheral Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 23/25] hw/arm/aspeed_ast10x0: Map HACE peripheral Cédric Le Goater
` (2 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Some SRAM appears to be used by the Secure Boot unit and
crypto accelerators. Name it 'secure sram'.
Note, the SRAM base address was already present but unused
(the 'SBC' index is used for the MMIO peripheral).
Interestingly using CFLAGS=-Winitializer-overrides reports:
../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides]
[ASPEED_DEV_SBC] = 0x7E6F2000,
^~~~~~~~~~
../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here
[ASPEED_DEV_SBC] = 0x79000000,
^~~~~~~~~~
This fixes with Zephyr:
uart:~$ rsa test
rsa test vector[0]:
[00:00:26.156,000] <err> os: ***** BUS FAULT *****
[00:00:26.157,000] <err> os: Precise data bus error
[00:00:26.157,000] <err> os: BFAR Address: 0x79000000
[00:00:26.158,000] <err> os: r0/a1: 0x79000000 r1/a2: 0x00000000 r2/a3: 0x00001800
[00:00:26.158,000] <err> os: r3/a4: 0x79001800 r12/ip: 0x00000800 r14/lr: 0x0001098d
[00:00:26.158,000] <err> os: xpsr: 0x81000000
[00:00:26.158,000] <err> os: Faulting instruction address (r15/pc): 0x0001e1bc
[00:00:26.158,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
[00:00:26.158,000] <err> os: Current thread: 0x38248 (shell_uart)
[00:00:26.165,000] <err> os: Halting system
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
[ clg: Fixed size of Secure Boot Controller Memory ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_ast10x0.c | 11 ++++++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 9a5e3c0bac..bd1e03e78a 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -71,6 +71,7 @@ struct AspeedSoCState {
AspeedSMCState spi[ASPEED_SPIS_NUM];
EHCISysBusState ehci[ASPEED_EHCIS_NUM];
AspeedSBCState sbc;
+ MemoryRegion secsram;
UnimplementedDeviceState sbc_unimplemented;
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
@@ -105,6 +106,7 @@ struct AspeedSoCClass {
const char *cpu_type;
uint32_t silicon_rev;
uint64_t sram_size;
+ uint64_t secsram_size;
int spis_num;
int ehcis_num;
int wdts_num;
@@ -143,6 +145,7 @@ enum {
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
ASPEED_DEV_SBC,
+ ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 1a06269cb1..592a19d988 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -21,7 +21,7 @@
static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SRAM] = 0x00000000,
- [ASPEED_DEV_SBC] = 0x79000000,
+ [ASPEED_DEV_SECSRAM] = 0x79000000,
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
[ASPEED_DEV_FMC] = 0x7E620000,
@@ -221,6 +221,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
&s->sram);
+ memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
+ sc->secsram_size, &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
+ &s->secsram);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -400,6 +408,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
sc->silicon_rev = AST1030_A1_SILICON_REV;
sc->sram_size = 0xc0000;
+ sc->secsram_size = 0x40000; /* 256 * KiB */
sc->spis_num = 2;
sc->ehcis_num = 0;
sc->wdts_num = 4;
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 23/25] hw/arm/aspeed_ast10x0: Map HACE peripheral
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (21 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 22/25] hw/arm/aspeed_ast10x0: Map the secure SRAM Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 24/25] hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F Cédric Le Goater
2023-01-19 12:34 ` [PATCH 25/25] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board Cédric Le Goater
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Since I don't have access to the datasheet, the relevant
values were found in:
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
Before on Zephyr:
uart:~$ hash test
sha256_test
tv[0]:hash_final error
sha384_test
tv[0]:hash_final error
sha512_test
tv[0]:hash_final error
[00:00:06.278,000] <err> hace_global: HACE poll timeout
[00:00:09.324,000] <err> hace_global: HACE poll timeout
[00:00:12.261,000] <err> hace_global: HACE poll timeout
uart:~$ crypto aes256_cbc_vault
aes256_cbc vault key 1
[00:00:06.699,000] <inf> hace_global: aspeed_crypto_session_setup
[00:00:06.699,000] <inf> hace_global: data->cmd: 1c2098
[00:00:06.699,000] <inf> hace_global: crypto_data_src: 93340
[00:00:06.699,000] <inf> hace_global: crypto_data_dst: 93348
[00:00:06.699,000] <inf> hace_global: crypto_ctx_base: 93300
[00:00:06.699,000] <inf> hace_global: crypto_data_len: 80000040
[00:00:06.699,000] <inf> hace_global: crypto_cmd_reg: 11c2098
[00:00:09.743,000] <inf> hace_global: HACE_STS: 0
[00:00:09.743,000] <err> hace_global: HACE poll timeout
[00:00:09.743,000] <err> crypto: CBC mode ENCRYPT - Failed
[00:00:09.743,000] <inf> hace_global: aspeed_crypto_session_free
uart:~$
After:
uart:~$ hash test
sha256_test
tv[0]:PASS
tv[1]:PASS
tv[2]:PASS
tv[3]:PASS
tv[4]:PASS
sha384_test
tv[0]:PASS
tv[1]:PASS
tv[2]:PASS
tv[3]:PASS
tv[4]:PASS
tv[5]:PASS
sha512_test
tv[0]:PASS
tv[1]:PASS
tv[2]:PASS
tv[3]:PASS
tv[4]:PASS
tv[5]:PASS
uart:~$ crypto aes256_cbc_vault
aes256_cbc vault key 1
Was waiting for:
6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
But got:
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[00:00:05.771,000] <inf> hace_global: aspeed_crypto_session_setup
[00:00:05.772,000] <inf> hace_global: data->cmd: 1c2098
[00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
[00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
[00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
[00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
[00:00:05.772,000] <inf> hace_global: crypto_cmd_reg: 11c2098
[00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
[00:00:05.772,000] <inf> crypto: Output length (encryption): 80
[00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_free
[00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_setup
[00:00:05.772,000] <inf> hace_global: data->cmd: 1c2018
[00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
[00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
[00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
[00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
[00:00:05.772,000] <inf> hace_global: crypto_cmd_reg: 11c2018
[00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
[00:00:05.772,000] <inf> crypto: Output length (decryption): 64
[00:00:05.772,000] <err> crypto: CBC mode DECRYPT - Mismatch between plaintext and decrypted cipher text
[00:00:05.774,000] <inf> hace_global: aspeed_crypto_session_free
uart:~$
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed_ast10x0.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 592a19d988..5c794c2420 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -28,6 +28,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SPI1] = 0x7E630000,
[ASPEED_DEV_SPI2] = 0x7E640000,
[ASPEED_DEV_UDC] = 0x7E6A2000,
+ [ASPEED_DEV_HACE] = 0x7E6D0000,
[ASPEED_DEV_SCU] = 0x7E6E2000,
[ASPEED_DEV_JTAG0] = 0x7E6E4000,
[ASPEED_DEV_JTAG1] = 0x7E6E4100,
@@ -165,6 +166,9 @@ static void aspeed_soc_ast1030_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
object_initialize_child(obj, "gpio", &s->gpio, typename);
+ snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
+ object_initialize_child(obj, "hace", &s->hace, typename);
+
object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
TYPE_UNIMPLEMENTED_DEVICE);
@@ -358,6 +362,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
}
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
+ /* HACE */
+ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ sc->memmap[ASPEED_DEV_HACE]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+
/* Watch dog */
for (i = 0; i < sc->wdts_num; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 24/25] hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (22 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 23/25] hw/arm/aspeed_ast10x0: Map HACE peripheral Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
2023-01-19 12:34 ` [PATCH 25/25] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board Cédric Le Goater
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
This SoC uses a Cortex-M4F. QEMU only implements a M4,
which is good enough. Add a TODO note in case the M4F
is added.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed_ast10x0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 5c794c2420..649b3b13c1 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -420,7 +420,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
dc->realize = aspeed_soc_ast1030_realize;
sc->name = "ast1030-a1";
- sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+ sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
sc->silicon_rev = AST1030_A1_SILICON_REV;
sc->sram_size = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 25/25] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board
2023-01-19 12:34 [PATCH 00/25] aspeed: Various extensions, fixes and cleanups Cédric Le Goater
` (23 preceding siblings ...)
2023-01-19 12:34 ` [PATCH 24/25] hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F Cédric Le Goater
@ 2023-01-19 12:34 ` Cédric Le Goater
24 siblings, 0 replies; 42+ messages in thread
From: Cédric Le Goater @ 2023-01-19 12:34 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Philippe Mathieu-Daudé, Peter Delevoryas,
Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Add a very quick test that runs some commands in a Zephyr shell:
$ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado
(2/2) tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephyros_1_07:
console: *** Booting Zephyr OS build v00.01.07 ***
console: ast1030_evb demo
console: SOC: AST1030-A1
console: uart:~$ kernel stacks
console: 0x36910 wdt_background (real size 1024): unused 988 usage 36 / 1024 (3 %)
console: 0x36ad8 shell_uart (real size 4096): unused 3084 usage 1012 / 4096 (24 %)
console: 0x2edb8 ADC0 (real size 400): unused 260 usage 140 / 400 (35 %)
console: 0x2f0f0 ADC1 (real size 400): unused 260 usage 140 / 400 (35 %)
console: 0x3b098 sysworkq (real size 1024): unused 860 usage 164 / 1024 (16 %)
console: 0x36cc0 usbdworkq (real size 1024): unused 860 usage 164 / 1024 (16 %)
console: 0x36bd8 usbworkq (real size 1024): unused 860 usage 164 / 1024 (16 %)
console: 0x36a10 logging (real size 768): unused 548 usage 220 / 768 (28 %)
console: 0x36ef8 idle 00 (real size 320): unused 268 usage 52 / 320 (16 %)
console: 0x47800 IRQ 00 (real size 2048): unused 1504 usage 544 / 2048 (26 %)
console: uart:~$ otp info scu
console: SCU BIT reg_protect Description
console: ____________________________________________________________________
console: 0x500 0x0 0x0 Disable ARM CM4 CPU boot (TXD5)
console: 0x500 0x1 0x0 /Reserved
console: 0x500 0x2 0x0 \ "
console: 0x500 0x3 0x0 Address offset of single chip ABR mode
console: 0x500 0x4 0x0 /Reserved
console: 0x500 0x5 0x0 | "
console: 0x500 0x6 0x0 | "
console: 0x500 0x7 0x0 | "
console: 0x500 0x8 0x0 | "
console: 0x500 0x9 0x0 | "
console: 0x500 0xA 0x0 | "
console: 0x500 0xB 0x0 | "
console: 0x500 0xC 0x0 | "
console: 0x500 0xD 0x0 | "
console: 0x500 0xE 0x0 | "
console: 0x500 0xF 0x0 | "
console: 0x500 0x10 0x0 \ "
console: 0x500 0x11 0x0 Disabl3 ARM JTAG debug
console: 0x500 0x12 0x0 /Reserved
console: 0x500 0x13 0x0 | "
console: 0x500 0x14 0x0 | "
console: 0x500 0x15 0x0 | "
console: 0x500 0x16 0x0 | "
console: 0x500 0x17 0x0 | "
console: 0x500 0x18 0x0 | "
console: 0x500 0x19 0x0 | "
console: 0x500 0x1A 0x0 | "
console: 0x500 0x1B 0x0 | "
console: 0x500 0x1C 0x0 | "
console: 0x500 0x1D 0x0 | "
console: 0x500 0x1E 0x0 | "
console: 0x500 0x1F 0x0 \ "
console: 0x510 0x0 0x0 /Reserved
console: 0x510 0x1 0x0 | "
console: 0x510 0x2 0x0 | "
console: 0x510 0x3 0x0 \ "
console: 0x510 0x4 0x0 Disable debug interfaces
console: 0x510 0x5 0x0 /Reserved
console: 0x510 0x6 0x0 | "
console: 0x510 0x7 0x0 \ "
console: 0x510 0x8 0x0 Enable boot from Uart5 by Pin Strap
console: 0x510 0x9 0x0 /Reserved
console: 0x510 0xA 0x0 \ "
console: 0x510 0xB 0x0 Enable boot SPI ABR
console: 0x510 0xC 0x0 Boot SPI ABR Mode
console: 0x510 0xD 0x0 /Boot SPI flash size
console: 0x510 0xE 0x0 | "
console: 0x510 0xF 0x0 \ "
console: 0x510 0x10 0x0 /Reserved
console: 0x510 0x11 0x0 | "
console: 0x510 0x12 0x0 | "
console: 0x510 0x13 0x0 | "
console: 0x510 0x14 0x0 | "
console: 0x510 0x15 0x0 \ "
console: 0x510 0x16 0x0 Enable boot SPI auxiliary control pins
console: 0x510 0x19 0x0 /Reserved
console: 0x510 0x1A 0x0 | "
console: 0x510 0x1B 0x0 | "
console: 0x510 0x1C 0x0 | "
console: 0x510 0x1D 0x0 | "
console: 0x510 0x1E 0x0 | "
console: 0x510 0x1F 0x0 \ "
console: 0x510 0x1E 0x0 Enable dedicate GPIO strap pins
console: 0x510 0x1F 0x0 Enable Secure Boot by Pin Strap
console: uart:~$ hwinfo devid
console: Length: 8
console: ID: 0x0000018000000180
console: uart:~$ crypto aes256_cbc_vault
console: aes256_cbc vault key 1
console: Was waiting for:
console: 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
console: ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
console: 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
console: f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
console: But got:
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
console: uart:~$ random get
console: 0x862460d
console: uart:~$ i2c scan I2C_0
console: 0 1 2 3 4 5 6 7 8 9 a b c d e f
console: 00: -- -- -- -- -- -- -- -- -- -- -- --
console: 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
console: 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
console: 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
console: 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
console: 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
console: 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
console: 70: -- -- -- -- -- -- -- --
console: 1 devices found on I2C_0
console: uart:~$ kernel uptime
console: Uptime: 9897 ms
console: uart:~$ kernel reboot warm
console: *** Booting Zephyr OS build v00.01.07 ***
PASS (1.08 s)
Ref: https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.07/Aspeed_Zephy_SDK_User_Guide_v00.01.07.pdf
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/avocado/machine_aspeed.py | 41 ++++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index 1cab946727..ddf05b3617 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -22,10 +22,11 @@ class AST1030Machine(QemuSystemTest):
timeout = 10
- def test_ast1030_zephyros(self):
+ def test_ast1030_zephyros_1_04(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:ast1030-evb
+ :avocado: tags=os:zephyr
"""
tar_url = ('https://github.com/AspeedTech-BMC'
'/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip')
@@ -41,6 +42,44 @@ def test_ast1030_zephyros(self):
exec_command_and_wait_for_pattern(self, "help",
"Available commands")
+ def test_ast1030_zephyros_1_07(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:ast1030-evb
+ :avocado: tags=os:zephyr
+ """
+ tar_url = ('https://github.com/AspeedTech-BMC'
+ '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip')
+ tar_hash = '40ac87eabdcd3b3454ce5aad11fedc72a33ecda2'
+ tar_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
+ archive.extract(tar_path, self.workdir)
+ kernel_file = self.workdir + "/ast1030-evb-demo/zephyr.bin"
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_file,
+ '-nographic')
+ self.vm.launch()
+ wait_for_console_pattern(self, "Booting Zephyr OS")
+ for shell_cmd in [
+ 'kernel stacks',
+ 'otp info conf',
+ 'otp info scu',
+ 'hwinfo devid',
+ 'crypto aes256_cbc_vault',
+ 'random get',
+ 'jtag JTAG1 sw_xfer high TMS',
+ 'adc ADC0 resolution 12',
+ 'adc ADC0 read 42',
+ 'adc ADC1 read 69',
+ 'i2c scan I2C_0',
+ 'i3c attach I3C_0',
+ 'hash test',
+ 'kernel uptime',
+ 'kernel reboot warm',
+ 'kernel uptime',
+ 'kernel reboot cold',
+ 'kernel uptime',
+ ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
+
class AST2x00Machine(QemuSystemTest):
timeout = 90
--
2.39.0
^ permalink raw reply related [flat|nested] 42+ messages in thread