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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id y17-20020ac85251000000b003b34650039bsm1975685qtn.76.2023.02.03.10.06.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Feb 2023 10:06:51 -0800 (PST) Message-ID: Date: Fri, 3 Feb 2023 19:06:49 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Content-Language: en-US To: Peter Maydell Cc: eric.auger.pro@gmail.com, richard.henderson@linaro.org, pbonzini@redhat.com, qemu-devel@nongnu.org References: <20230203171657.2867598-1-eric.auger@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 2/3/23 19:04, Peter Maydell wrote: > On Fri, 3 Feb 2023 at 17:17, Eric Auger wrote: >> Many registers whose 'cooked' writefns induce TLB maintenance do >> not have raw_writefn ops defined. If only the writefn ops is set >> (ie. no raw_writefn is provided), it is assumed the cooked also >> work as the raw one. For those registers it is not obvious the >> tlb_flush works on KVM mode so better/safer setting the raw write. >> >> Signed-off-by: Eric Auger >> Suggested-by: Peter Maydell >> >> --- >> >> I'am not familiar with those callbacks. I have tested in kvm accelerated >> mode including migration but I fail to test with TCG. It SIGSEVs for >> me even without my additions. I am not sure whether the .raw_writefn >> must be set only for registers only doing some TLB maintenance or >> shall be set safely on other registers doing TLB maintenance + other >> state settings. >> --- >> @@ -718,16 +718,20 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = { >> * the unified TLB ops but also the dside/iside/inner-shareable variants. >> */ >> { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, >> - .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, >> + .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, >> + .writefn = tlbiall_write, .raw_writefn = raw_write, >> .type = ARM_CP_NO_RAW }, > Anything with type ARM_CP_NO_RAW shouldn't need a .raw_writefn, because > that type indication says that it's a bug if we ever call > read_raw_cp_reg() or write_raw_cp_reg() on it. (Specifically, > for KVM, we should never end up trying to do a raw read/write > for a state sync because write_list_to_cpustate() and > write_cpustate_to_list() skip NO_RAW cpregs.) OK thanks for the info. I will respin accordingly. Eric > > thanks > -- PMM >